Aldec Active-HDL 10.4.183.6396 (FPGA及ASIC设计和验证环境)

  • 软件大小|Size:1.12G
  • 软件语言|Language:英文
  • 运行环境|Platform:/Win7/8/10
  • 使用方式|License:浮动License
  • 更新时间|Release:2018-05-13
  • 软件评价|Rank:
  • 历史版本|Version:Aldec Active-HDL 9.2/10.2/10.3
  • 下载次数|Counts:
  • 标 签|Tag:Aldec   Active-HDL   

软件介绍|Description ——介绍来源于互联网,具体功能以官方为准。

Active-HDL是集成VHDL,Verilog,EDIF,System C开发环境。它由设计工具,VHDl&Verilog编译器,单仿真内核,调试工具,图形仿真和资源、库等管理工具,可让用户运行仿真,综合,实现,以及第三方工具。

Aldec公司所提供的高阶FPGA及ASIC设计和验证环境—Active-HDL,能够协助工程人员进行电信、军事,或者消费性电子等应用的硬体实现。Active-HDL能够和业界标准相容,如IEEE、ISO、IEC及其它标准等,它为您的设计提供了极广的覆盖率及支援。 其它强大的功能和工具,如程式码覆盖率分析(Code Coverage Analysis),图表编辑器,和状态图表编辑器,都能协助您以非平行的方式检视您的设计元素。Active-HDL具备除错工具,能支援Soft或Hard IP Core元件;其它的特色如图形化使用介面、程式语法、或混合模式开发都能加快您的设计速度。

Aldec Active-HDL 10.3
Aldec Active-HDL 10.3 32&64Bit—FPGA及ASIC设计和验证环境

The Active-HDL suite is a comprehensive and totally integrated environment for digital IC design and verification that employs hardware description languages and C/C++ solutions. It provides engineers and design teams with tools for efficient and vendor independent design implementation and testing. The Active-HDL suite has been designed based on customer suggestions and feedbacks to ensure highest design productivity and remarkable ease-of-use.

Active-HDL supports even the most complex FPGA and ASIC designs by providing the following key features:

  • Design Entry
  • Compiler
  • High Performance Simulator
  • Debugging
  • Co-simulation
  • Automated Testbench Generation
  • Design Data Management
  • FPGA Vendor Support
  • Coverage and Profiler Metrics
  • Documentation
  • Legacy Design Support
  • Actel Solutions
  • Compiler
  • High Performance Simulator
  • Debugging
  • Co-simulation
  • Automated Testbench Generation
  • Design Data Management
  • FPGA Vendor Support
  • Coverage and Profiler Metrics
  • Documentation
  • Legacy Design Support
  • Actel Solutions

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