电子电路 第4页

CoventorMP将Coventor行业领先的MEMS设计软件工具CoventorWare 10.301和MEMS + 6.301的优势结合到了一个强大的MEMS设计自动化环境中。新平台提供了一个全面的环境，其中可以输入一次设计，并用于创建高精度有限元模型（CoventorWare）和高效紧凑有限元模型（MEMS +）。
CoventorMP平台为MEMS设计提供了一个统一的环境，从完全参数化的设计入门到生产可在各个抽象级别进行仿真的功能模型。实质上，在CoventorMP中输入的设计可以作为所有类型建模的单一“黄金主人”，无需在不同的建模环境之间进行耗时且容易出错的手动传输。

CoventorMP combines the complementary strengths of Coventor’s industry-leading software tools for MEMS design, CoventorWare 10.2 and MEMS+ 6.2, into a single powerful environment for MEMS design automation. The new platform provides a comprehensive environment where designs can be entered once and used to create highly accurate finite element models (CoventorWare) and highly efficient compact finite element models (MEMS+).
The CoventorMP platform provides a unified environment for MEMS design, starting from fully parametric design entry to the production of functional models that can be simulated at all levels of abstraction. In essence, designs entered in CoventorMP can serve as a single “golden master” for all types of modeling, eliminating the need for time consuming and error-prone manual transfer between different modeling environments.
Life cycle cost, the sum of non-recurring and recurring costs (energy, maintenance)

Language: English
Operating Systems: Windows 7/8.x/10.x 64Bit

Cadence Spectre Circuit Simulator(原MMSIM)为模拟、射频（RF）和混合信号电路提供快速，准确的SPICE级仿真。它与CadenceVirtuoso定制设计平台紧密集成，可在多个域中提供详细的晶体管级分析。其卓越的架构允许低内存消耗和高容量分析。

特征
– 提供开箱即用的高性能，高容量SPICE级模拟和RF仿真，以实现准确性和融合
– 通过适用于最复杂的模拟和定制数字IC的用户友好型仿真设置，实现精度和性能之间的权衡
– 使用+ postlayout选项，通过RLCK寄生效应提供高效的布局后仿真
– 利用高效的多线程技术提高仿真吞吐量
– 模拟使用S参数模型（n端口）和有损耦合传输线（mtline）元素建模的分布式组件
– 对周期性稳态和调制信号进行RF分析，用于测量频谱响应，增益压缩，互调失真，阻抗匹配，稳定性，隔离和ACPR
– 包括先进的统计分析（Smart Monte Carlo，DCmatch，High Sigma Yield Estimation），以提高先进工艺节点IC的可制造性和良率，同时不会牺牲产品上市时间
– 与Virtuoso ADE产品套件紧密集成，提供快速交互式仿真设置，交叉探测，可视化和仿真结果的后处理
– 采用硅精密，代工厂认证的设备型号，广泛的代工支持可确保高设计质量

Cadence Spectre Circuit Simulator provides fast, accurate SPICE-level simulation for analog, radio frequency (RF), and mixed-signal circuits. It is tightly integrated with the Cadence Virtuoso® custom design platform and provides detailed transistor-level analysis in multiple domains. Its superior architecture allows for low memory consumption and high-capacity analysis.

Features
– Provides high-performance, high-capacity SPICE-level analog and RF simulation out of the box for accuracy and convergence
– Enable the tradeoff between accuracy and performance through user-friendly simulation setup applicable to the most complex analog and custom-digital ICs
– Uses the +postlayout option to provide efficient post-layout simulation with RLCK parasitics
– Utilizes efficient multi-threaded technology to improve simulation throughput
– Simulates distributed components modeled using S-parameter models (n-port) and lossy coupled transmission line (mtline) elements
– Performs RF analysis of periodic steady-state and modulated signals used to measure spectral response, gain compression, inter-modulation distortion, impedance matching, stability, isolation, and ACPR
– Includes advanced statistical analysis (Smart Monte Carlo, DCmatch, High Sigma Yield Estimation) to improve the manufacturability and yield of ICs at advanced process nodes without sacrificing time to market
– Tight integration with the Virtuoso ADE Product Suite provides fast interactive simulation set-up, cross-probing, visualization, and post-processing of simulation results
– Wide foundry support ensures high design quality using silicon-accurate, foundry-certified device models

Language: English
Operating Systems: RHEL 5.x

FEST3D能够高效地分析波导技术中的各种无源RF结构。
基本上，FEST3D基于矩量法有效解决的积分方程技术。
此外，采用边界积分 – 共振模式扩展（BI-RME）方法提取具有任意截面的复杂波导的模态图。这些方法的成功组合确保了高度的准确性，并减少了计算资源（就CPU时间和内存而言）。
在此基础上，FEST3D能够在极短时间内（几秒或几分钟）模拟复杂的无源器件，而通用软件（基于分段技术，如有限元或有限差分）可花费数小时计算。
此外，与模式匹配技术不同，FEST3D采用的电磁算法将相对收敛的问题最小化，从而获得更可靠的结果。此外，积分方程技术提取部分频率相关计算，因此与标准模式匹配技术相比，每个频率点的计算时间更短。当需要多种模式来精确分析组件时，这种好处更加明显。

Aurora FEST3D 2018 SP2 x64 (无源RF结构分析) | 1009 Mb

FEST3D is able to efficiently analyse different kind of passive RF structures in waveguide technology.
Basically, FEST3D is based on an integral equation technique efficiently solved by the Method of Moments.
Additionally, the Boundary Integral-Resonant Mode Expansion (BI-RME) method is employed for extracting the modal chart of complex waveguides with arbitrary cross-section. The successful combination of such methods ensures a high degree of accuracy, as well as reduced computational resources (in terms of CPU time and memory).
On this basis, FEST3D is able to simulate complex passive devices in extremely short times (of the order of seconds or few minutes), whereas general purpose software (based on segmentation techniques such as finite elements or finite differences) can spend hours for the same calculations.
Moreover, unlike mode-matching techniques, the electromagnetic algorithms employed in FEST3D minimize the problems of relative convergence leading to more confident results. Furthermore, the integral equation technique extracts part of the frequency dependent computations, thus allowing a faster computational time per frequency point when compared to standard mode-matching techniques. This benefit is more evident when many modes are required for an accurate analysis of the component.

Language: English
Operating Systems: Windows 7/8.x/10 64Bit

Electromagnetic Professional（EMPro）是 Keysight EEsof EDA 的软件设计平台，用于分析元器件的三维电磁场（EM）效应，例如高速和射频 IC 封装、封装接线、天线、芯片上和芯片外嵌入式无源元件以及 PCB 互连设备。EMPro 具有现代领先的设计、仿真和分析环境以及大容量仿真技术，并综合了业界领先的射频和微波电路设计环境――先进设计系统（ADS），可用于快速高效地进行射频和微波电路设计。

EMPro 的主要优势

– 设计流程整合：通过使用电磁场电路仿真，创建可以在先进设计系统（ADS）中使用二维电路版图以及原理图进行仿真的三维元器件。
– 广泛的仿真技术：使用频域和时域三维电磁场仿真技术设置和运行分析：有限元方法（FEM）和时域有限差分法（FDTD）
– 高效的用户接口：使用现代的、简单的图形用户界面快速创建任意三维结构，该界面可以节省时间并提供先进的脚本特征
– Electromagnetic Professional（EMPro）是一个三维电磁场仿真平台，可以创建和导入任意三维结构，并运行有限元方法（FEM）和有限差时域（FDTD）仿真。EMPro 是设计流程综合解决方案的一部分，该方案还包括先进设计系统（ADS）电路设计环境和多电磁场仿真技术。

主要特性

高效的现代三维固态建模环境
– 可以从头开始或使用现有模板创建任意三维对象
– 可以导入、修改和仿真 CAD 文件
– 功能强大的 Python 脚本可提供先进的自动化功能
– 支持 Linux 和 Windows

与 ADS 设计流程整合
– 可以导出参数化三维元器件，并结合原理图/版图在 ADS 环境中进行仿真
– 可从 ADS 导入版图对象

频域仿真
– 有限元方法（FEM）仿真引擎
– 最适合典型射频/微波元器件仿真
– 针对不同应用的直接或迭代求解器
– EMPro 和 ADS 可提供相同的 FEM 引擎

时域仿真
– 时域有限差分（FDTD）仿真引擎
– 最适合天线仿真等大型电子问题以及信号完整性应用
– 一致性测试选件可用于比吸收率（SAR）等常规分析
– 图形处理器单元（GPU）加速选件可大幅提升速度和容量。

Keysight Technologies Inc. has released an update to EMPro 2017. This release delivers several FEM mesher and solver improvements resulting in faster simulations, as well as new parameterization capabilities, enhanced visualization and improved python scripting.
Electromagnetic Professional (EMPro) is Keysight EEsof EDA’s electromagnetic (EM) simulation software design platform for analyzing the 3D EM effects of components such as high-speed and RF IC packages, bondwires, antennas, on-chip and off-chip embedded passives and PCB interconnects. EMPro EM simulation software features a modern design, simulation and analysis environment, high capacity simulation technologies and integration with the industry’s leading RF and microwave circuit design environment, Advanced Design System (ADS) for fast and efficient RF and microwave circuit design.

Key Benefits of EMPro EM Simulation Software
– Design Flow Integration: Create 3D components that can be simulated together with 2D circuit layouts and schematics within ADS, using EM-circuit cosimulation
– Broad Simulation Technology: Set up and run analyses using both frequency-domain and time-domain 3D EM simulation technologies: Finite Element Method (FEM) and Finite Difference Time Domain (FDTD)
– Efficient User Interface: Quickly create arbitrary 3D structures with a modern, simple GUI that saves time and our EMPro EM simulation software provides advanced scripting features

Language: English
Operating Systems: Windows 7/8.x 64Bit

SystemVue 2018 是用于电子系统级（ESL）设计的专用电子设计自动化（EDA）环境，可支持系统架构师和算法开发人员在无线和航空航天与国防通信系统的物理层上进行创新设计，为射频、DSP 和 FPGA/ASIC 的设计人员提供独特的价值。SystemVue 作为 ESL 设计和信号处理的专用平台，可替代通用的数字、模拟和数学环境。SystemVue 可提供射频信息，从而将物理层研发和验证时间缩短一半，并能够与您的主流 EDA 流程建立关联。

SystemVue 的主要优势
– 当今基带/物理层环境中最佳的射频保真度–支持基带设计人员对射频进行虚拟化处理并消除多余裕量
– 与测试的完美结合可增强设计在实际应用中的成熟度，并简化基于模型的设计流程–从体系结构的建立到验证
– 适合网络化工作组的价格，可增进设计的重复使用，同时充分加强基带和射频设计团队的协作

Keysight Technologies, Inc. introduced the latest release of its powerful SystemVue 2018 software. This release now includes dynamic plotting, and provides many improvements to the core platform, design flows, and add-on libraries.

SystemVue is a focused electronic design automation (EDA) environment for electronic system-level (ESL) design. It enables system architects and algorithm developers to innovate the physical layer (PHY) of wireless and aerospace/defense communications systems and provides unique value to RF, DSP, and FPGA/ASIC implementers. As a dedicated platform for ESL design and signal processing realization, SystemVue replaces general-purpose digital, analog, and math environments. SystemVue “speaks RF”, cuts PHY development and verification time in half, and connects to your mainstream EDA flow.

Language: English/简体中文/Multilingual
Operating Systems: Windows 7/8.x 64Bit

全球电子设计创新领导者Cadence Design Systems公司发布了更新的（06.17.721_Hotfix）IC 06.17.700 Virtuoso。 Virtuoso工具套件有助于集成电路的全定制设计。该套件提供各种设计和验证工具，可为不同的设计要求提供完整的前端到后端解决方案，例如全定制集成电路和数字集成电路。

关于Cadence Virtuoso系统设计平台。
Cadence Virtuoso系统设计平台是一个基于系统的整体解决方案，提供从单一原理图驱动IC和封装的LVS清洁布局的功能。有两个关键流程：实施和分析。

实现流程用于在Virtuoso原理图编辑器中创建IC封装原理图，然后将原理图数据传输到Cadence SiP布局以布局物理设计。此外，该流程还提供生成和验证库零件，输出物料清单（BOM）以及执行布局与原理图（LVS）检查的功能。

无论布局设计状态如何，分析流程都用于提取和模拟系统的任何部分（IC-package-PCB）。此外，该流程还能够自动生成PCB和IC封装布局的原理图，将IC封装的实例绑定到ICschematic或模型，并使用Virtuoso ADE ProductSuite和Spectre多模仿真构建测试平台以模拟系统接口。从PCB和IC封装布局中提取的Cadence Sigrity模型会自动拼接到生成的原理图中。

IC 06.17.700附带的独立软件：
– Virtuoso Power System L (IC6.1.7)
– Voltus-Fi Custom Power Integrity Solution XL IC6.1.7
– Dracula Design Rule Checker (4.9)
– Dracula Layout Vs. Schematic Verifier (4.9)
– Dracula Parasitic Extractor(4.9)
– Dracula Physical Verification Suite(4.9)
– Dracula Physical Verification and Extraction Suite (4.9)
– Virtuoso Chip Assembly Router (11.3)

Cadence Design Systems, Inc., the leader in global electronic design innovation, has released an updated (06.17.721_Hotfix) IC 06.17.700 Virtuoso. The Virtuoso suite of tools facilitates the full-custom design of integrated circuits. The suite offers a wide range of design and verification tools that provide complete front-to-back solutions for varying design requirements, such as full-custom integrated circuits and digital integrated circuits.

About Cadence Virtuoso System Design Platform.
The Cadence Virtuoso System Design Platform is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean layout of ICs and packages from a single schematic. There are two key flows: implementation and analysis.

The implementation flow is used to create an IC package schematic in Virtuoso Schematic Editor and then transfer the schematic data to Cadence SiP Layout to layout the physical design. In addition, this flow offers the capability to generate and verify library parts, output a bill of materials (BOM), and perform layout versus schematic (LVS) checking.

The analysis flow is used to extract and simulate any portion of the system (IC-package-PCB) regardless of the layout design status. Moreover, this flow offers the capability to automatically generate schematics for the PCB and IC package layouts, bind the instances of the IC package to the ICschematic or models, and build testbenches to simulate the system using the Virtuoso ADE ProductSuite plus Spectre Multi-Mode Simulation interface. Cadence Sigrity models extracted from the PCB and IC package layouts get automatically stitched into the generated schematic.

Standalone Software Shipped with IC 06.17.700:
– Virtuoso Power System L (IC6.1.7)
– Voltus-Fi Custom Power Integrity Solution XL IC6.1.7
– Dracula Design Rule Checker (4.9)
– Dracula Layout Vs. Schematic Verifier (4.9)
– Dracula Parasitic Extractor(4.9)
– Dracula Physical Verification Suite(4.9)
– Dracula Physical Verification and Extraction Suite (4.9)
– Virtuoso Chip Assembly Router (11.3)

Language: English
Operating Systems: RHEL 5.x-7.x

R3D是一种电阻式3D提取和分析产品，适用于功率器件等大型电阻结构。效率和可靠性是关键的设计标准，R3D提供了计算和优化两者的解决方案。
提供的电流密度，电位分布和灵敏度分析使用户能够快速识别其设计的关键区域，并改进电迁移和IR Drop的设计，从而提高可靠性。
通过使用Rdson和RC分布式网表，可以快速实现效率提升，从而降低静态和开关损耗。
R3D能够优化金属布局，检测器件位置，键合焊盘和金属开槽，进一步提高效率和可靠性。

F3D是基于随机随机游走法的3D电容和分布式RC提取器。 F3D使用原始布局配置从第一原理计算电容，包括与65nm，45nm工艺等相关的所有3D和高级制造效果。 F3D应用包括模拟，AMS，IP和数字设计，这些设计需要非常精确的寄生数据来驱动时序，噪声和电气分析签核解决方案。

R3D is a resistive 3D extraction and analysis product for large resistive structures like power devices. Efficiency and reliability are key design criteria and R3D provides a solution to calculate and optimize both.
The current density, potential distribution and sensitivity analysis provided, allows users to quickly identify the critical areas of their design and improve the design for electromigration and IR Drop, improving reliability.
By using Rdson and the RC distributed netlist, efficiency improvements are quickly achievable, reducing both static and switching losses.
R3D provides the ability to optimize metal layouts, sense device location, bondpads and metal slotting, further improving the efficiency and reliability.

F3D is a 3D capacitance and distributed RC extractor based on stochastic random walk method. F3D calculates capacitances from first principles using the original layout configuration, including all 3D and advanced manufacturing effects associated with 65nm, 45nm processes, and beyond. F3D applications include Analog, AMS, IP and Digital designs which require very accurate parasitic data to drive timing, noise, and electrical analysis sign-off solutions.

Language: English
Operating Systems: RHEL 4.x-6.x

Mentor Questa Verification IP（QVIP）可在任何模拟器上无缝集成到所有高级验证环境中。凭借跨所有协议的一致且易于使用的UVM架构，QVIP确保了块级，子系统和SoC设计验证的最大生产力和灵活性。
Questa VIP 库可向工程师提供标准 UVM SystemVerilog (SV) 组件，而这些元件使用的通用架构包括了所有支持的协议。因此可允许在一个验证团队内快速部署多个协议。测试计划、符合性测试、测试序列和协议覆盖范围都作为 SV 和 XML 源代码包含在内，从而允许简单复用、扩展和调试。Mentor VIP组件还包含一整套协议检查、错误注入和调试功能。
今天的设计严重依赖于越来越多的复杂行业标准接口协议。通过将Mentor的协议和方法专业知识构建到支持许多行业标准接口的可重用组件库中，QVIP使工程师能够有效地处理这种复杂性，提高质量并缩短调度时间。
这使工程师无需花时间开发BFM，验证组件或VIP，因此他们可以专注于设计的独特和高价值方面。
大型协议和内存模型库
QVIP支持大型行业标准协议和存储器接口和设备库。它包括标准的SystemVerilog UVM组件，使用一致的通用架构，允许在验证团队中快速部署和共享多个协议和内存模型。测试计划，一致性测试，测试序列和协议覆盖都包含在SystemVerilog和XML源代码中，允许轻松重用，扩展和调试。所有QVIP组件都包含一整套协议检查，错误注入和调试功能。

Mentor Questa Verification IP (QVIP) integrates seamlessly into all advanced verification environments on any simulator. With a consistent and easy-to-use UVM architecture across all protocols, QVIP ensures maximum productivity and flexibility for the verification of block level, subsytem, and SoC designs.
Today’s designs rely heavily on a growing variety of complex industry standard interface protocols. QVIP enables engineers to effectively deal with this complexity, improves quality, and reduces schedule time by building Mentor’s protocol and methodology expertise into a library of reusable components that support many industry standard interfaces.
This frees engineers from spending time developing BFMs, verification components, or VIP, so they can focus on the unique and high-value aspects of their designs.
Large Library of Protocols and Memory Models
QVIP supports a large library of industry-standard protocol and memory interfaces and devices. It includes standard SystemVerilog UVM components using a consistent, common architecture that allows rapid deployment and sharing of multiple protocols and memory models within a verification team. Test plans, compliance tests, test sequences, and protocol coverage are all included as SystemVerilog and XML source code, allowing easy reuse, extension, and debug. All QVIP components include a comprehensive set of protocol checks, error injection, and debug capabilities.

Language: English/简体中文/Multilingual
Operating Systems: Windows 7/8.x 64Bit/RHEL 5.x-7.x

Questa Ultra验证平台支持将设计验证从TLM加速到RTL再到片上应用的验证过程。所以，它可帮助用户将高效验证技术用于复杂的设计。Questa Ultra验证平台集成了仿真和相关技术，用以处理智能测试平台自动化、低功耗验证和验证管理等问题。QuestaUltra验证平台也与用于跨时钟域（CDC）和形式验证的专业化技术紧密结合，解决通常难以覆盖到的设计问题。
Questa Ultra提供了强大的验证基础和广阔的视野，涵盖了模拟、仿真以及用以解决日益增长的验证问题的形式验证。它对于开放式行业标准、可定制性和可扩展性的领先支持也确保了最佳的验证流程，能够实现最高的生产效率、进度的可预见性和加速验证流程。

Questa Ultra delivers a 10X improvement in time to coverage. Integrating simulation with intelligent testbench automation, Questa Ultra eliminates redundancy in randomized testbenches, reducing the amount of time and workstation resources required to hit coverage targets. Questa Ultra further extends the Questa Prime version to include UPF (unified power format) support for power aware simulation and verification, along with integrated intelligent testbench automation.

Questa Ultra includes the Questa inFact and Questa Core/Prime application software.

New Core/Prime Features
The following new features are available in the 10.7 release series. VM indicates that the feature is contained in the Verification Management Tools and PA indicates Power Aware Simulation
• Improved VHDL performance – memories, clocks, composites
• Improved SystemVerilog performance, stability, support
• Gate Level add_seq_delay and other optimizations
• Improved access write performance
• Early access support of IEEE 1735 version 2 cryptography
• Improved coverage adaptive exclusions, reporting consistency
• Power Aware performance, new reports, more UPF3.0 support (PA)
• Deprecated old -novopt flow, option to be removed in next release

New inFact Features
The release v10.6a contains the following new features:
Packed Array Enhancements
inFact IDE and TBI supports:
• Use of a meta_action with an explicit bit-width that can be accessed as a packed array within a foreach constraint, similar to bit vector in System Verilog. For more information, see Array of meta_actions in Questa inFact User’s Manual.
• Use of System Verilog built-in function $countones().The countones function is a constraint expression that counts the number of one-bits in the scalar value.

Testbench Import (TBI) Enhancements
New TBI switches added for controlling the unrolling of arrays in infact cmd import_testbench:
• [-disable_unroll_array struct-type | struct-type::array]
• [-enable_unroll_array struct-type | struct-type::array]
QSA Batch Mode Enhancements
• QSA Batch Mode is an operational mode that allows you analyze and get the results of analysis without invoking the GUI.You need to specify an input CSV file for QSA
arguments and get results from the output CSV file. For more information, see QSA in Batch Mode in
• New QSA command line arguments added: -batch, -analysis_spec, -o, and -v. For more information, see QSA Command Line Arguments in Questa inFact User’s Manual.
QSA GUI Mode Enhancements
• Added File Menu options in QSA GUI mode. The File selection from the main menu lets you open configuration file in CSV format, save the configuration file, save the
result in a .out file, and exit QSA.
• QSA Source Viewer – you can view SystemVerilog source code directly from the QSA Interface.You can double-click the variable or constraint to open the source code with
the highlighted variable or constraint in the source code.

Language: English
Operating Systems: RHEL 6.x-7.x

Mentor Graphics ModelSim是业界最优秀的HDL语言仿真器，它提供最友好的调试环境，是唯一的单内核支持VHDL和Verilog混合仿真的仿真器。是作FPGA/ASIC设计的RTL级和门级电路仿真的首选，它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段。全面支持VHDL和Verilog语言的IEEE 标准，支持C/C++功能调用和调试
具有快速的仿真性能和最先进的调试能力，全面支持Windows 64位平台。
主要特点：
RTL和门级优化，本地编译结构，编译仿真速度快；
单内核VHDL和Verilog混合仿真；
源代码模版和助手，项目管理；
集成了性能分析、波形比较、代码覆盖等功能；
数据流ChaseX；
Signal Spy；
C和Tcl/Tk接口，C调试

ModelSim eases the process of finding design defects with an intelligently engineered debug environment.
The ModelSim debug environment efficiently displays design data for analysis and debug of all languages. ModelSim allows many debug and analysis capabilities to be employed post-simulation on saved results, as well as during live simulation runs.

Features

• Multi-language, high performance simulation engine
• Verilog, VHDL, SystemVerilog Design
• Code Coverage
• SystemVerilog for Design
• Integrated debug
• JobSpy Regression Monitor
• Mixed HDL simulation option
• SystemC Option
• TCL/tk
• 32 and 64-bit platform support — Linux, Windows

Benefits

• High performance HDL simulation solution for FPGA & ASIC design teams
• The best mixed-language environment and performance in the industry.
• Intuitive GUI for efficient interactive or post-simulation debug of RTL and gate-level designs
• Merging, ranking and reporting of code coverage for tracking verification progress
• Sign-off support for popular ASIC libraries
• All ModelSim products are 100% standards based. This means your investment is protected, risk is lowered, reuse is enabled, and productivity is enhanced.
• Award-winning technical support

Language: English
Operating Systems: Windows 7/8.x/10/RHEL 6.x-7.x