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STEAG EBSILON Professional 13.02 with VTU-GT-Lib Program 5.1 & VTU-GT-Lib Data 6.0

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Ebsilon软件是STEAG公司实际应用开发的软件,是电站工程的一站式解决方案。广泛地用于电站设计、评估和优化及其他热力循环过程。在设计过程中,有助于识别优化的循环、评估多个选项和可替代结构;在电站运行过程中,评估损失和建议可行的电站改进。通过引入特别参数到模型中,为你的应用预期设计一个性能优化的电站。
EBSILON Professional 13是 STEAG能源服务推出EBSILON Professional最新版,EBSILON是一种用于热力循环过程的通用仿真系统:用于规划,设计和优化工厂的极其精确的工具,已经系统地增强了近30年。EBSILON具有功能附加模块的创新系统基于热力循环过程的建模,并在效率和部分负载行为方面可靠地评估它们。它绘制了电力工程设备的新电路和现有电路,包括传统发电厂,核电站和太阳能发电厂,海水淡化厂和燃料电池应用。EBSILONProfessional的强大优势在于开放透明的软件结构和极快的系统参数计算。


STEAG EBSILON Professional 13.02 (热力系统计算仿真)| 1.0 Gb

STEAG Energy Services is pleased to announce the availability of EBSILON Professional V13, is a universal simulation system for thermodynamic cycle processes: an extremely precise tool for the planning, design, and optimization of plants that has been systematically enhanced for almost 30 years.

About STEAG EBSILON Professional. The innovative system with its functional additional modules is based on the modeling of thermodynamic cycle processes and evaluates them reliably with regard to efficiency and partial load behavior. It maps new and existing circuits of power engineering plants, including conventional power plants, nuclear and solar power plants, desalination plants and fuel cell applications. The great strengths of EBSILON®Professional lie in the open and transparent software structure and the extremely fast calculation of the system parameters.

That’s what EBSILON Professional can do

– Convenient analysis and presentation of results
– Intuitive modeling with graphical user Interface
– Comprehensive component and material data libraries are available
– Intelligent fault analysis and online help
– Open software architecture and powerful Interfaces
– Multilingual user interface and documentation (German, English, French, Spanish, Turkish and Chinese)

HomePage:http://www.steag-systemtechnologies.com/
Language: English/简体中文/Multilingual
Operating Systems: Windows 7/8.x

Advanced Design System (ADS) 2019 x64

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Advanced Design System(ADS)是领先的电子设计自动化软件,适用于射频、微波和信号完整性应用。ADS 是获得商业成功的创新技术(例如 X 参数*和 3D 电磁仿真器)的代表,这些技术已被无线通信与网络以及航空航天与国防领域中的领先厂商广泛采用。对于 WiMAX™、LTE、多千兆位/秒数据链路、雷达和卫星应用,ADS 能够借助集成平台中的无线库以及电路系统和电磁协同仿真功能提供基于标准的全面设计和验证。

ADS 的主要优势
快速、精确、简单易用的全套集成系统、电路和电磁仿真器,能够一次性成功完成桌面流程设计。
特定应用设计指南将长期积累的专业知识应用于简单易用的界面中。

ADS 2017 为充满挑战的无线通信设计提供了 3D 解决方案和更多解决方案,其中包括:

  • 3D 版图查看、路由选择和编辑
  • 多技术 3D 电热仿真
  • 利用 Python 数据链路进行 3D 数据可视化
  • 使用 FEM 进行更强大的 3D 电磁仿真
  • 3D Via Designer:支持访问精确的过孔模型
  • 自动建立线圈等器件的 PCell 结构
  • 用于分层管理的新选件
  • 改善的互操作性
  • SOA 支持更好的可靠性
  • 增强的电路仿真性能

ADS 2017 为信号完整性(SI)和电源完整性(PI)设计所提供的最新特性和功能包括:

  • PIPro——为供电网络提供直流电热仿真
  • PIPro——提供为去耦合电容器和电感器优化的材料清单
  • 3D Via Designer:支持访问精确的参数化差分过孔模型
  • 提高了 IBIS 模型可用性,并提供最新的 IBIS 封装模型组件
  • 极大提升瞬态和通道仿真速度,以便加速批量仿真和高端口数 S 参数测量
  • 统计通道仿真(Sim)更新,以支持 PAM4 IBIS-AMI 模型
  • 在表格视图中进行基片编辑

Advanced Design System (ADS) 2019 x64 (电子设计自动化) | 2.0 Gb

Keysight Technologies Inc. pleased to announce the release of Advanced Design System (ADS) 2017. This release introduces a host of new 3D capabilities and enhanced performance in the areas of circuit, electromagnetic (EM), and electro-thermal simulation, all packed into a single simulation platform.
Advanced Design System 2019 Release Notes:
Feature Updates

Simulation
– Signal Integrity/Power Integrity
– Silicon RFIC Interoperability
– EM Simulation
– FEM Performance and Parallel Simulation
– EM Usability (EM for Everyone)
– Circuit Simulation Performance
– Electro-Thermal
– Dynamic Link
Design Environment
– Layout and Schematic Editing
– Technology and Substrates
– 3D Layout Design
– 3D Viewing, Routing and Editing
– 3D FEM Simulation Performance
– 3D Data Visualization
– 3D Electro-Thermal Simulation
– Printing
Verification and Manufacturing Artwork
– Layout Versus Schematic (LVS)
– Design Rule Checker (DRC)
– Assura DRC Link
– Artwork Translators
– PCB Links
Design Enablers
– CoilSys
– Encrypted iRCX support
– Data Flow
– Examples
– PDKs
General Enhancements
– Licensing amd Installation
– Ultra High Resolution Screen
– Quick Start and Getting Started
– ADS Exports from BenchVue

Language: English
Operating Systems: Windows 7/8.x 64Bit

Altair FluxMotor 2018.1.0 x64

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FluxMotor2018是一款功能强大的电子设备生产加工软件,可以帮助您设计马达、发动机、齿轮等多种类型的动力设备,软件提供一个仿真模块,可以将您自己设计的图形加载到软件上生产CAD模型,利用几何扫描的技术,直接将您绘制的图形转换为可以编辑修改的2D、3D模型,从而加速设计的效率,Altair FluxMotor 2018提供自动化测试功能,当您在仿真环境中模拟设备运行的时候,软件会根据测试的部分,生成一份专业的报告,快速评估设备存在的问题,为后期的开发提供安全保障。
FluxMotor 与低频电磁和热仿真的领先软件 Flux 都是 Altair HyperWorks CAE 套件的一部分。该软件工具可帮助用户利用标准和自定义部件来设计和创建电机模型,以及直观地添加绕组和材料以便进行一系列测试并对比电机性能。
FluxMotor 是一款易于使用而且高效的预设计工具,适合与电机相关的各个领域的设计者。这款软件面向旋转电机设计者和制造商等各类用户,让电机专业人员能够在数分钟内快速定义电机并评估其技术经济潜力。FluxMotor 高效的工作环境可确保更好的电机性能可视化效果,并使得计算快速准确,还能够将计算结果连接到 HyperWorks 套件中的 Flux 有限元软件和其他工具,以进行更多高级研究,包括多物理场优化功能等。
FluxMotor 的软件优势包括:

  • 动态库提供多种标准或自定义选项,直接应用于电机建模。
  • 促进项目管理,有助于快速访问过往研究并管理所有产品。
  • 计算方法充分利用有限元建模的强大能力。
  • 自动运行工作流提供了以用户为导向的高效环境,适合不同层级的用户。

FluxMotor 的功能:

  • 该设计环境带有专用接口,有助于电机设计人员在数分钟内快速地为电机设计定型。
  • 4 种不同的绕组模式有助于用户找到合适的绕组结构。
  • 部件库主要用于直观查看和选择部件;提供标准库。
  • 标准部件、磁性元件和槽均可编辑与自定义。
  • 材料数据库全面且可扩展。
  • 自动的标准和相关测试,可随时进行。
  • 电机库便于管理电机和项目,帮助用户对机器进行分类,并可以快速查看过往研究。

Altair FluxMotor 2018.1.0 x64 (电机预设计工具)| 1.0 Gb

Altair announces the release of FluxMotor 2018.0, a dedicated platform focusing on the pre-design of electric rotating machines.
Here is the list of new major features:
– Improvement of internal processes of optimization
– Three new tests available with sine wave drive:
. Computation of a working point targeted with Current, Control angle and Speed (I,, N)
. Computation of a working point targeted with Torque and Speed (T, N)
. Computation of a working point targeted with current and voltage (I, U)
– First available test available with the Square wave drive:
. Computation of a working point targeted with a forced current (I-Forced) – Parameterized trapezoidal shape
– Macro function to build rotor parts (magnets) from the Flux2D environment sketcher (part built with the sketcher or import from a CAD file)
– New parts are available in Part Library

Note: For the full list of new and improved features, please refer to the release notes located in the folder of your Altair FluxMotor 2018 or here here

Language: English
Operating Systems: Windows 7/8.x 64Bit


Download Link (下载地址)
Altair_FluxMotor_2018.1.0_x64.part1
Altair_FluxMotor_2018.1.0_x64.part2

Synopsys Library Compiler 2018.06 SP1 Linux64

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Synopsys Library Compiler工具可以从文本中读取ASIC库类型并将其编译为内部数据库(.db格式)或VHDL库。
编译的数据库支持synthesis工具,VHDL库支持VHDL仿真工具。
Library Compiler的作用是生成两种类型的库,支持Synopsys合成和模拟产品。这两种类型的库是
Synthesis库
综合库由技术库,物理库和符号库组成,其中包含描述ASIC组件所需的信息类型:技术和物理特性以及原理图符号。
•技术库包含有关ASIC库中每个组件的特征和功能的信息。存储在技术库中的信息包括区域,时序,功能等。 Synopsys设计工具使用此信息做出综合决策。
•符号库包含有关表示每个ASIC组件的原理图符号的信息,以及有关特殊符号的信息,例如页面边框和表外连接器。然后,您可以使用Design Analyzer工具
•生成设计原理图
•在计算机屏幕上显示原理图
•使用PostScript绘图仪或打印机绘制设计
•有关物理库的信息,请参阅库编译器物理库
VHDL模拟ASCII库
Library Compiler可以生成VHDL库,其中包含模拟所需的时序和功能信息。


Synopsys Library Compiler 2018.06 SP1 Linux64 (库编译工具)| 517 Mb

The Library Compiler tool from Synopsys reads the description of an ASIC library from a text file and compiles the description into either an internal database (.db format) or into VHDL libraries.
The compiled database supports synthesis tools. The VHDL libraries support VHDL simulation tools.
The role of Library Compiler is to generate two types of libraries that support Synopsys synthesis and simulation products. The two types of libraries are
Synthesis Libraries
The synthesis libraries consist of the technology libraries, physical libraries, and symbol libraries that contain the types of information required to describe ASIC components: technical and physical characteristics and schematic symbols.
• Technology libraries contain information about the characteristics and functions of each component in an ASIC library. Information stored in the technology libraries consists of area, timing, function, and so on. The Synopsys design tools use this information to make synthesis decisions.
• Symbol libraries contain information about the schematic symbols that represent each ASIC component, as well as information about special symbols, such as page borders and off-sheet connectors. Using the Design Analyzer tool, you can then
• Generate schematics of designs
• Display the schematic on the computer screen
• Draw the designs, using your PostScript plotter or printer
• For information about physical libraries, see the Library Compiler Physical Libraries
VHDL Simulation ASCII Libraries
Library Compiler can generate VHDL libraries that contain the timing and functional information needed for simulation.

Language: English
Operating Systems:RHEL 6.x-7.x 64Bit

Cadence Stratus High-Level Synthesis 17.10 Linux

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Cadence Stratus High-Level Synthesis (HLS)作为整个SoC设计中使用的第一个高级综合平台,它的效率比传统RTL设计高出10倍。基于超过14年的HLS生产部署,Stratus工具可让您从抽象的SystemC,C或C ++模型中快速设计和验证高质量的RTL实现。使用该平台,您可以将知识产权(IP)开发周期从几个月缩短到几周。

使用Stratus HLS,您可以使用其集成设计环境(IDE)轻松创建抽象模型,并从这些模型中合成优化的硬件。然后,您可以将这些模型重新定位到新技术平台,并且比传统的手工编码RTL更容易重复使用它们。您可以在HLS环境中主动在功率,区域和性能之间进行权衡。

主要优势



  • 通过更高级别的抽象提高生产力

  • 通过高级优化和探索改进QoR

  • 通过使用行为IP实现更广泛的IP重用


Cadence Stratus High-Level Synthesis 17.10 Linux (高阶综合工具)| 1.2 Gb

Cadence Stratus High-Level Synthesis (HLS) is a first high-level synthesis platform for use across your entire SoC design,it delivers up to 10X better productivity than traditional RTL design. Based on more than 14 years of production HLS deployment, the Stratus tool lets you quickly design and verify high-quality RTL implementations from abstract SystemC, C, or C++ models. Using the platform, you can reduce the intellectual property (IP) development cycle from months to weeks.
With Stratus HLS, you can easily create abstract models using its integrated design environment (IDE) and synthesize optimized hardware from those models. You can then retarget these models to new technology platforms and reuse them more easily than you could traditional hand-coded RTL. You can actively make tradeoffs between power, area, and performance from within the HLS environment.

Key Benefits


     

  • Improves productivity through a higher level of abstraction
  •  

  • Improves QoR through high-level optimizations and exploration
  •  

  • Enables broader IP reuse through use of behavioral IP
  •  

HomePage: http://www.cadence.com
Language: English
Operating Systems: RHEL 6.x-7.x

Dorado Twaker 1108.2016c Linux

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Tweaker Tweaker作为业界主流的ECO自动优化工具,其采用了独特的ECO 技术架构,并基于设计的静态时序分析和布局布线等sign-off数据,对设计进行ECO domain的划分,对设计进行局部的、增量的且安全的MMMC优化。Tweaker在优化的过程中充分考虑Physical Aware及Power Aware特性, 显著地降低迭代时间和减少额外错误被引入的机会。
主要功能优势:
– 采用MMMC技术在一次运行中实现多种ECO优化
– Minimum ECO logic专利技术算法
– 单一License可覆盖超过200种应用场景(scenarios)
– 基于Physical Aware与Power Domain Aware(CPF/UPF)的优化策略
– 基于signoff数据采用局部、增量和安全的优化分析
– 支持主流的静态时序分析工具与布局布线工具
– 支持跨越设计边界的ECO优化
– 超过500次成功tape-out验证,工艺涵盖110nm到7nm
– 友好的GUI提供高效的分析及手动ECO能力


Dorado Twaker 1108.2016c Linux (ECO自动优化工具)| 45 Mb

Dorado Tweaker is fundamentally architected for ECO incremental jobs. It relies on the signoff quality input data to perform “local optimization” which focuses only on the critical parts of the design. The approach minimizes the turnaround time, correlation issues, and the impact to the performance, while maximizing the tool capacity.
It nclude:
Timing ECO – Tweaker-T1
Power ECO – Tweaker-P1 Leakage Power Optimization
Functional ECO – Tweaker-F1
Metal ECO – Tweaker-M1

Language: English
Operating Systems: RHEL 5.x-7.x

ANSYS Electromagnetics Suite 19.0 Linux64

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Ansys电磁仿真套件Electromagnetics(原来的Ansoft)
ANSYS是电磁仿真软件行业的引领者,供应从电路级到系统级的仿真工具。工程师可依靠我们的系统仿真产品和电磁场求解器来设计通信和网络系统、集成电路(ICs)、印制板(PCBs)及机电系统。
ANSYS信号完整性设计软件是设计高速串行通道、并行总线及现代高速电子设备中完整电力分配系统的理想工具。
我们的射频、微波和天线设计软件可以帮助工程师设计、仿真和验证通信系统、移动设备、计算机、无线电和雷达中的高频组件和天线。
机电、电力电子和机电一体化工具是完成汽车、航空航天和工业自动化市场中组件和系统设计的行业标准。


ANSYS Electromagnetics Suite 18.1/19.0 Linux64 (电磁仿真套件) | 1.75G

ANSYS Electromagnetics providing new, unique capabilities and enhancements that offer the most advanced approach to guide and optimize product designs.
ANSYS is the leading provider of electromagnetic simulation software, engineers rely on our electromagnetic field solvers and system simulation products to design communication and networking systems, integrated circuits (ICs), printed circuit boards (PCBs) and electromechanical systems.
ANSYS signal integrity analysis products are ideal for designing high-speed serial channels, parallel buses and complete power delivery systems found in modern high-speed electronic devices.
Our RF and Microwave design and simulation software enables engineers to design, simulate and validate high-frequency components and antennas found in communication systems, mobile devices, computers, radio and radar.
ANSYS electromechanical simulation software is ideal for the design of electromechanical and power electronics components and systems common to the automotive, aerospace and industrial automation industries.

Language: English
Operating Systems:RedHat Entrprise Linux 5.x-7.x 64Bit


Synopsys SiliconSmart 2017.12 SP2 Linux64

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SiliconSmart ADV是一种综合性标准单元库特性表征和品质保证(QA)解决方案,这种改进型解决方案可以生成PrimeTIme签核品质库,并在可用计算资源上提供最大的吞吐量。SiliconSmart ADV独特的授权许可方法可以轻松地适应不同的工作任务量,从而免去了特性表征团队的负担,使他们无须去预测未来的工作量要求以及在传统的繁琐授权许可方法限制下操作。此外,创新性SiliconSmart技术利用内嵌的黄金参考SPICE引擎,来为生成先进的LibertyTM模型提供特性表征加速,PrimeTIme静态时序分析(STA)使用该模型来准确地解释超低电压FinFET工艺对时序的影响。这包括PrimeTIme参数片上变异(POCV)、先进的波形传播(AWP)和电迁移(EM)分析。
SiliconSmart ADV通过一个同一许可证,提供了最先进标准单元库的库特性表征和品质保证所需的一切东西。为了实现最佳的准确性和最快的吞吐量,SiliconSmart ADV包括内嵌的Synopsys FineSim SPICE和Synopsys HSPICE电路仿真解决方案。它还提供灵活的多核许可来优化大型计算中心环境中的吞吐量,并轻松地适应不断变化的特性表征需求。SiliconSmart ADV综合性的LVF特性表征和建模性能实现了一流的PrimeTIme POCV变异分析。智能LVF性能优化技术提供最高的吞吐量和准确性。为了支持单元层EM特性表征,对最新的Liberty EM模型扩展的支持也被包括了进来。SiliconSmart ADV还提供一套工具加速签核品质库的手工执行及易于出错的品质保证过程。整个库认证过程将自动进行并行化处理,以提供快速的周转时间并尽早确定问题。可视化的辅助措施和智能化组织产生的结果有助于快速隔离问题区域,并提供品质保证管理度量指标。


Synopsys SiliconSmart 2017.12 SP2 Linux64 (ADV单元库特性表征解决方案)| 640 Mb

SiliconSmart is a comprehensive characterization solution for standard cells, I/O, complex cells and memory. It generates accurate model libraries tightly correlated with Synopsys’ digital implementation tools. Its built-in FineSim; simulation technology and tight integration with the gold-standard HSPICE; circuit simulator enable characterization and signoff accuracy. SiliconSmart supports all of the standard models, including NLDM (non-linear delay model), CCS (composite current source) and AOCV (advanced on-chip variation) models.
Benefits

  • SiliconSmart’s precise characterization and modeling capability combined with HSPICE golden accuracy is critical for producing signoff-quality library models, including timing, power, signal integrity and OCV to ensure best PrimeTime accuracy during static timing and power analysis. This unique platform-level integration of SiliconSmart produces the best correlation between PrimeTime and HSPICE for advanced technology nodes

Comprehensive solution

  • SiliconSmart is a comprehensive, unified solution that generates libraries for standard cells, I/Os and complex cells, such as multi-bit flip-flops and memories

High performance with pre-characterization optimization

  • SiliconSmart increases performance by using innovative pre-characterization optimization and intelligent optimization techniques that reduce the number of simulation runs required during the library characterization phase

Advanced node-ready

  • SiliconSmart is ready for characterizing and modeling libraries at advanced technology nodes, such as 16-nm and 14-nm. It supports generation of POCV coefficients and supports the latest FinFET models

Language: English
Operating Systems:RHEL 5.x-7.x 64Bit

Synopsys SpyGlass 2017.12 SP2 Linux64

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SpyGlass平台针对VERILOG和VHDL用先进的静态和动态分析来检查和诊断设计中可能存在的潜在问题,然后用其分析和追踪引擎来追踪问题的根源,最后给出一个解决问题的方法和建议。SpyGlass能够指出SOC问题中的非常复杂的问题,例如跨时钟域问题、同步问题以及SOC设计中的集成问题。并且,SpyGlass还可以检查电子设计规则(ERC)来确保设计符合工业设计标准或者用户自己定义的标准。

SpyGlass还提供了四个功能强大的选项:
(一)SpyGlass CDC提供了业界最完整的多时钟域解决方案,能自动识别各种同步手段(包括HandShake,FIFO),能采用Formal引擎验证同步方法在功能上的正确性。
(二)SpyGlass Constraints帮助设计人员在设计的整个流程中生成,验证和管理他们的约束文件。
(三)SpyGlass DFT提供了能够预测ATPG的测试覆盖率分析的能力,基于这个选项,用户可以很容易地预计所作设计的可测试性并且利用工具提供的指导来提高设计的可测试性。
(四)SpyGlass LowPower能够让用户能够快速分析出设计中的功耗效率问题,从而在还没有达到后端工序的情况下快速地进行功耗的优化,在power estimate工具中,用户甚至可以在不进行逻辑综合和物理实现的情况下对功耗进行量化的计算。


Synopsys SpyGlass 2017.12 SP2 Linux64 (Verilog检查工具)| 640 Mb

SpyGlass use many advanced algorithms and analysis techniques, provides designers with insight about their design, early in the process at RTL. It functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.
Spyglass is an important platform of Synopsys RTL verification solution that provides complete static analysis to ensure all aspects of the design are optimized before implementation such as Lint, CDC, Power, Constraints, DFT/DSM etc.

Language: English
Operating Systems: RHEL 5.x-7.x 64Bit

Synopsys Custom Compiler 2017.12-SP1 Linux64

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Custom Compiler将定制设计任务时间由数天缩短至数小时,消弭了FinFET的生产力差距。为了将FinFET版图生产力提升到新的高度,Synopsys采用了新颖的定制设计方法,即开发视觉辅助自动化技术,从而提高普通设计任务的速度,降低迭代次数并支持复用。通过与行业领先的客户的密切合作,Custom Compiler已经在最先进的节点上进行生产工作,并通过行业领先的工厂获得了FinFET工艺技术的支持(参看今天新闻辅稿)。许多Custom Compiler用户将于今天在圣塔克拉拉会议中心开幕的硅谷Synopsys用户群大会上分享各自的经验。

视觉辅助自动化

Custom Compiler Assistants可提高生产力,它利用版图设计人员所熟悉的图形使用模式,无需编写复杂代码和约束条件,无需额外设置,Custom Compiler即可自动处理日常和重复性工作。Custom Compiler提供了四种辅助功能:Layout、In-Design、Template和Co-Design。

· Layout Assistants通过可视觉引导的自动布局及绕线提高了设计速度。该款绕线器是连接FinFET阵列和大型M型晶体管的首选。它可以自动克隆连接并创建 pin tap。用户仅使用鼠标就可引导绕线器,由Custom Compiler自动完成绕线细节。设计人员可以使用创新方法进行器件布局。该方法允许用户持续优化,在提供布局选择的同时使版图设计人员能够完全控制结果,无需预先输入任何文本约束条件。

· In-Design Assistants通过在验收验证前捕捉物理和电气错误,降低成本高昂的设计迭代次数。Custom Compiler包括速度极快并始终保持激活状态的嵌入式设计规则检查(DRC)引擎。另外,Custom Compiler还内建电迁移检查以及电阻和电容提取引擎。与其他“电感知”工具不同,Custom Compiler的提取功能基于Synopsys黄金标准的StarRC™内核。

· Template Assistants帮助设计人员复用现有知识累积,使之轻松将之前的版图决策用于新的设计。Template Assistants实际上可以通过Layout Assistants的布局器和绕线器从已完成的工作中自动学习知识。Template Assistants智能识别与先前完成的电路类似的电路,并支持用户将相同的版图和绕线模式当作模板用于新的电路。Custom Compiler出厂时加载了一套内置常用电路模板,如电流镜、电平位移器和差分对。

· Co-Design Assistants将IC Compiler™和Custom Compiler合并为统一的定制和数字实现解决方案。用户可以自由地在Custom Compiler与 IC Compiler之间来回切换,使用各自的指令持续完成自己的设计。利用Co-Design Assistants,IC Compiler用户可以在任何实现阶段对其数字设计执行全定制编辑。同样地,Custom Compiler用户可以利用IC Compiler在自己的定制设计中实施数字实现流程。Co-Design Assistants的无损多次往返功能可确保跨所有数字和定制数据库同步所有变更。

Custom Compiler基于行业标准Open Access数据库,提供包括电路图、模拟分析与版图的开放环境。Custom Compiler结合Synopsys的电路仿真、物理验证以及数字实施工具,提供了一种全面的定制设计解决方案。


Synopsys Custom Compiler 2017.12-SP1 Linux64 (定制设计解决方案)| 2.757 Gb

Custom Compiler is Synopsys’ full-custom solution that features the pioneering visually-assisted automation flow that speeds up custom design tasks, reduces iterations and enables reuse. Tuned for rapid implementation of FinFET custom designs, it shortens the time it takes to complete FinFET custom design tasks from days to hours. Its visually-assisted automation flow leverages the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.

Highlights
– Template Assistants help designers reuse existing custom layout know-how
– In-Design Assistants reduce iterations with native design rule checks and parasitic extraction
– Layout Assistants speed up layout tasks with user-guided placement and routing
– Co-Design Assistants unify custom and digital flow to accelerate mixed-signal IC design

Language: English
Operating Systems: RHEL 5.x-7.x 64Bit