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Synopsys Synplify FPGA 2018.03 SP1 Win/Linux

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Synplify FPGA包含可选Synplify Pro和Synplify Premier FPGA综合工具。
Synopsys Synplify FPGA设计软件提供了一个高品质,高性能和易于使用的FPGA实现和调试环境。采用Synopsys的FPGA工具套件增益设计师快速进入超结果为复杂的FPGA,面积优化成本和降低功耗,自动化软错误缓解,分层设计能力和多FPGA厂商的支持。该的Synplify Pro和Synplify Premier FPGA设计工具,通过提供链接到高性能功能验证与VCS仿真和集成Synphony模型编译器的信号处理硬件的高层次综合提供额外的价值。
许多设计和验证团队越来越倾向于使用基于 FPGA 的原型验证,以便使产品及时进入市场。 基于 FPGA 的 Synopsys 原型验证解决方案可以使开发者尽早进行芯片制造前的嵌入式软件开发和软硬件协同设计,从而缩短上市时间并降低昂贵的器件改版费用。 同时,我们紧密集成且易于使用的HAPS硬件和软件工具套件可大幅加快从单个 IP 模块到处理器子系统再到整个SoC的软件开发、软硬件集成和系统验证。


Synopsys Synplify FPGA 2017.09/2018.03 SP1 Win/Linux (FPGA综合工具) | 1097 Mb

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Synplify Premier solution is the industry’s most productive FPGA implementation and debug environment. It includes all the features of Synplify Pro and additionally provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes.
The Synplify Premier software delivers fast turnaround time capabilities and feedback for users seeking to quickly implement the design on the board or to tune their design projects prior to final implementation. It addresses the most challenging aspects of FPGA design including timing closure and has the ability to perform graph-based physical synthesis for more accurate upfront timing prediction. It provides flows for fast logic verification and RT-Level debug. Under the hood, it contains optimization techniques that enhance DSP, IP and embedded design results. For ASIC prototypers, it delivers ASIC design file and DesignWare compatibility as well as tight integration with the Confirma Rapid Prototyping platform and FPGA vendor back-end tools as well as vendor embedded tools including Altera SoPC Builder and Xilinx EDK.
The Synplify Premier product offers FPGA Designers and ASIC Prototypers, targeting single FPGA-based prototypes, with the most efficient method of design implementation and debug. The Synplify Premier software provides in-system verification of FPGAs, dramatically accelerates the debug process, and provides a rapid and incremental method for finding elusive design problems.
The Synplify Premier software advantages include:
* technology and vendor independence
* in-system debug
* fast timing closure
* RTL analysis
* DSP-friendly synthesis algorithms
* superior Quality of Results (QoR)

Language: English
Operating Systems: Windows 7/8.x/10.x/RHEL 6.6+, 7.x/SLES 11.x and 12.x

NI AWR Design Environment with Analyst 14.0.9138 x64

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NI AWR Design Environment v14在设计流程管理和仿真中引入了许多创新,支持单片微波集成电路(MMIC),RFIC,多芯片模块和印刷电路板(PCB)技术。 模拟功能已在Microwave Office APLAC谐波平衡(HB)和Visual System Simulator(VSS)系统级仿真引擎中得到扩展,并且AXIEM平面3D和Analyst任意3D电磁(EM)解算器 。
多芯片模块的设计自动化和仿真已得到增强,在单个项目中更多地支持多技术工艺设计套件(PDK),对OpenAccess(原理图)数据库的新支持以及对Spectre RFIC网络表的APLAC协同仿真支持,以及简化的EM布局和端口创建。对于PCB设计,新的导入向导支持ODB ++和IPC2851数据库,以提供与主流第三方PCB布局工具的互操作性。还增加了新的布局编辑功能,以及简化的多技术管理。此外,V14中的新型EM Socket II架构为来自ANSYS,CST和Sonnet的AWR连接合作伙伴解决方案提供了改进的第三方EM仿真流程,使设计人员能够访问NI AWR设计环境中的备用EM仿真器
V14通过用于5G候选调制波形和相控阵行为模型增强的新通信库提供的高度精确的模拟RF前端组件测量来满足特定的系统要求。 RF功率放大器设计人员现在可以使用VSS中的系统级负载拉动分析为通信性能度量(如邻道功率比(ACPR)和误差矢量幅度(EVM))生成轮廓。 RF滤波器设计人员可以利用iFilter综合工具中的新功能加速其产品开发,并且被动和控制组件(如变压器,耦合器和混频器)的设计人员可以从新的综合功能和强大的新的优化方法中受益,使用专有的遗传算法更坚固的设计。


NI AWR Design Environment with Analyst 14.0_9067 x64 (高频电路和微波系统设计)| 321 Mb


NI AWR Design Environment v14 introduces numerous innovations in design flow management and simulation, supporting monolithic microwave integrated circuit (MMIC), RFIC, multi-chip module and printed circuit board (PCB) technologies. Simulation capabilities have been expanded within the Microwave Office APLAC harmonic balance (HB) and Visual System Simulator (VSS) system-level simulation engines and speed improvements have been made to both its AXIEM planar 3D and Analyst arbitrary 3D electromagnetic (EM) solvers.
Design automation and simulation have been enhanced for multi-chip modules, with greater support for multi-technology process design kits (PDKs) within a single project, new support for OpenAccess (schematic) databases and APLAC co-simulation support for Spectre RFIC netlists, as well as simplified EM layout and port creation. For PCB design, a new import wizard supports ODB++ and IPC2851 databases to provide interoperability with mainstream third-party PCB layout tools. New layout editing capabilities have also been added, along with simplified multi-technology management. Furthermore, the new EM Socket II architecture within V13 offers improved third-party EM simulation flows for AWR Connected partner solutions from ANSYS, CST and Sonnet, giving designers access to alternate EM simulators within NI AWR Design Environment.
V14 addresses specific system requirements with highly accurate simulated RF front-end component measurements provided through new communication libraries for 5G candidate modulation waveforms and phased-array behavioral model enhancements. RF power amplifier designers can now use the system-level load-pull analysis in VSS to generate contours for communication performance metrics such as adjacent channel power ratio (ACPR) and error vector magnitude (EVM). RF filter designers can take advantage of new capabilities in the iFilter synthesis tool to accelerate their product development and designers of passive and control components such as transformers, couplers and mixers can benefit from the new synthesis capabilities and powerful new optimization methods using proprietary genetic algorithms for more robust designs.

Language: English
Operating Systems: Windows 7/8.x/10 64Bit


Download Link (IDM下载)
NI AWR Design Environment 13.02

Mentor Graphics Tanner Tools With HyperPX 2016.2 x64

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Tanner EDA Tools是一款功能强大的集成电路设计软件,主要功能包括数模混合电路、模拟电路和MEMS设计等,在电路设计、版图设计和仿真验证方面带来了很大的帮助,可以满足专业人员的需求。目前版本是Tanner EDA Tools 2016.2 Update1.

软件特点
– 完整的模拟/数模混合IC全定制设计组件
– OpenAccess,LEF/DEF,Liberty和SDF数据格式支持
– 支持多重抽象级网表仿真:行为级、模块级、门级
– 调试和验证支持System Verilog, Verilog, Verilog-AMS, Verilog-A和VHDL等语言
– 提供内建的库导航器,有效跨越自顶向下和自底向上的层次化设计查看单元视图
– 自顶向下的混合信号仿真
– 已验证的,与综合兼容的DFT支持
– 高速时序分析
– 全角度版图编辑
– 实时DRC检查,DRC和LVS验证与Calibre工具兼容
– 使用SDL加速版图设计,可进行自动布局布线,支持HSPICE, PSPICE, Verilog和CDL等格式数据导入
– 支持参数化cell,称为T-cell,可用于可编程接口操作(UPI),创建自动化宏
– HiPer DevGen可实现参数化器件生成版图
– 支持多Foundry工艺
– 提供多语言菜单(英语,日语,简体中文、繁体中文,德语,意大利语和俄语等)


Tanner Tools 2016.2 Update1 With HyperPX x64 (集成电路设计)| 546 Mb

Mentor Tanner Tools 2016.2 provides electronic design automation (EDA) software used by companies in a wide variety of industries. Its solutions enable designers to move rapidly from concept to silicon by enabling the design, layout, and verification of analog/mixed-signal ICs, ASICs, and MEMS.
Tanner EDA solutions offer designers the perfect combination of price and performance to meet any design challenge. The company’s solutions include tools for:

  • Schematic Capture: S-Edit
  • Simulation: T-Spice, W-Edit
  • Physical Layout: L-Edit
  • Verification: HiPer Verify, L-Edit Standard DRC, L-Edit LVS and more
  • Parasitic Layout Extraction: HiPer PX, 2D and 3D parasitic layout extraction

These scalable solutions have a range of applications in the biomedical, consumer electronics, next-generation wireless, imaging, power management, and RF market segments.

Language: English/简体中文/Multilingual
Operating Systems: Windows 7/8.x 64Bit

Aldec Riviera-PRO 2018.02 x64/Linux64

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Aldec Riviera的混合语言VHDL、Verilog和SystemVerilog HDL编译器与C/C++编译器内核的直接连接,提供了无缝的SystemC协同仿真环境,这种连接以前只能通过慢速的PLI/VPI等接口通信实现。Riviera 允许工程人员通过设计与验证工具建立SystemC模块,并采用外部C编译器进行编译和协同仿真,仿真结果可在Riviera的Waveform Viewer/Editor中进行检验。 除协同仿真外,SystemC还为配合SystemC验证库(SCV)使用的处理级(transaction-level)测试平台开发提供了条件,设计人员通过SystemC可在短期内创建更可靠的测试平台,其处理级的执行速度比事件驱动的测试平台快100倍以上。
Riviera为系统级验证工程人员提供了几个采用HDL的SystemC设计样例。由于多数系统设计人员比较熟悉C++,SystemC为传统硬件工程师与系统工程师之间建立了快速沟通。然而,如果缺乏必要的培训,多数工程人员对其还难以掌握。
由于Riviera将C++中的面向硬件的结构以一个标准C++类库的形式提供,支持SystemC为用户提供了很大便利,该软件利用软硬件操作的概念实现了大跨度的设计和验证。SystemC提供了一个可互操作建模的平台,能实现快速的系统级C++模型开发与交换,此外还为系统级工具的开发提供了一个稳定的平台。


Aldec Riviera-PRO 2018.02 Win/Linux x64 | 298 Mb

Aldec Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

Language: English
Operating Systems: Windows 7/8.x/10.x/RHEL 5.x-7.x 64Bit


Tensilica Xtensa Xplorer 7.0.9 Linux

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Cadence Xtensa Xplorer是Tensilica Xtensa处理器的集成开发环境。Xtensa Xplorer允许芯片架构师通过快速描述其处理器所需的关键指令,存储器和外设接口功能,快速探索替代设计方法。
Xtensa Xplorer软件包包括以下内容:
– Xtensa Xplorer,包括TIE开发,处理器配置和软件开发功能
– Xtensa Tools的当前版本,包括软件开发,建模和TIE开发功能
– Xplorer示例演示了Xtensa处理器的功能,包括用于软件开发的示例Xtensa处理器配置构建


Tensilica Xtensa Xplorer 7.0.9 Linux (集成开发环境)| 1.1 Gb

Cadence Xtensa Xplorer is a integrated Development Environment for Tensilica Xtensa Processors.Xtensa Xplorer allows chip architects rapidly explore alternative design approaches by quickly describing the key instruction, memory, peripheral interface functions required by their processor.
Xtensa Xplorer package includes the following:
– Xtensa Xplorer, including TIE development, processor configuration and software development capabilities
– The current version of Xtensa Tools including software development, modeling and TIE development capabilities
– Xplorer samples that demonstrate features of Xtensa processors, including an example Xtensa processor configuration build for software development

Language: English
Operating Systems: RHEL 5.x-7.x

Cadence INCISIVE 15.20.001 Linux

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Cadence设计系统公司是全球电子设计创新的领导者,它推出了其领先的功能验证平台和方法INCISIVE 15.20。Integrated Metrics Center(IMC)和Incisive Enterprise Manager(vManager)可用
随着所有细分市场中的电子产品变得越来越复杂,开发其底层硬件和软件以及整合双方,电子产品将继续变得更加复杂。早期的软件开发,硬件验证,硬件/软件集成和集成系统验证已成为主要挑战,增加了开发成本,项目进度和风险。
使用Cadence Verification Suite,您可以将系统集成时间缩短高达50%,从而加速知识产权(IP)开发,片上系统(SoC)集成以及并发硬件/软件开发。该验证套件由核心引擎,验证结构技术和跨这些技术的解决方案组成.。
核心引擎包括JasperGold形式验证,RocketSim和Incisive仿真,Palladium®仿真和Protium FPGA原型设计。我们开发了每台发动机,以提供一流的技术。
验证结构技术包括验证IP,Incisive vManager规划和指标,Indago调试解决方案以及Perspec软件驱动的测试。我们开发了这些技术以提供流驱动的多引擎验证环境。
该套件中的解决方案包括最短项目进度的总吞吐量,公制驱动的质量签收,以及以应用为中心的重点,以满足移动,网络和服务器,汽车,消费者和物联网(IoT)产品的需求,航空航天和国防以及其他垂直领域。
我们的Verification Suite技术,流程和解决方案支持广泛的行业标准,可供第三方集成,并由我们的生态系统合作伙伴(包括ARM和许多其他合作伙伴)进一步增强。


Cadence INCISIVE 15.20.001 Linux (模型质量检验)| 13.5 Gb

Cadence Design Systems, Inc., a leader in global electronic design innovation, introduced its leading functional verification platform and methodologies, INCISIVE 15.20.
As electronic products across all market segments become more sophisticated, developing their underlying hardware and software, and integrating the two sides, continues to grow more complex. Early software development, hardware verification, hardware/software integration, and integrated system validation have become primary challenges, increasing development costs, project schedules, and risks.
Using the Cadence Verification Suite, you can reduce system integration time by up to 50%, accelerating intellectual property (IP) development, system-on-chip (SoC) integration, and concurrent hardware/software development. This verification suite is comprised of core engines, verification fabric technologies, and solutions spanning these technologies, as shown in Figure 1.
Core engines include JasperGold formal verification, RocketSim and Incisive simulation, Palladium® emulation, and Protium FPGA prototyping. We developed each engine to provide best-in-class technology.
Verification fabric technologies include Verification IP, Incisive vManager planning and metrics, Indago debug solutions, and Perspec software-driven testing. We developed these technologies to provide a flow-driven multi-engine verification environment.
Solutions in the suite include total throughput for the shortest project schedule, metric-driven signoff for quality, and an application-centric focus to meet the needs of products for mobile, networking and servers, automotive, consumer and the Internet of Things (IoT), aerospace and defense, and other vertical segments.
Our Verification Suite technologies, flows, and solutions support a broad range of industry standards, are open for third-party integration, and are further augmented by our ecosystem partners, including ARM and many others.

Language: English
Operating Systems: RHEL 5.x-7.x

Keysight Model Builder Program (MBP) 2017.2 x64

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Model Builder Program (MBP) 2017 介绍了用于静态随机存取存储器(SRAM)单元的新模型提取套件。自动化模型提取流程针对静态模型和紧凑模型进行了增强,包括 BSIM3v3、BSIM4 和 BSIM-CMG。Script API 获得更新,可以支持更多功能。用户界面(UI)也进行了众多改进。内部 SPICE 引擎支持最新的模型版本:BSIM-CMG 110.0、109.0,BSIM-IMG 102.8、102.7,HiSIM2 2.9.0,HiSIM_HV 2.3.2、2.3.1、2.3.0 和 EKV 302.00。


Keysight Model Builder Program (MBP) 2017.2 x64 (模型质量检验)| 775 Mb

Model Builder Program (MBP) is a one-stop solution that provides both automation and flexibility for high-volume model generation. MBP includes automated extraction packages for industry standard models as well as an open interface for modeling strategy customization. Turnkey solutions are also provided for the advanced statistical and mismatch model extraction, layout proximity effects (LPE) modeling, static random access memory (SRAM) cell modeling, HVMOS modeling, scalable Inductor modeling and corner library generation.

Key Benefits of MBP
– Automated extraction packages and the internal engine to increase modeling productivity.
– Script environment to increase the flexibility for customization.
– User friendly GUI and a rich set of modeling utilities to further increase the working efficiency and improve model quality.

Language: English
Operating Systems: Windows 7/8.x 64Bit


Keysight Model Builder Program (MBP) 2017.2 x64 – 复制到IDM高速下载
http://dl.downloadly.ir/Files/Software2/MBP_2017_Update2_x64_Downloadly.ir.rar

Keysight Model Quality Assurance (MQA) 2017.2 x64

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Model Quality Assurance(MQA)是一款自动化的 SPICE 模型验证软件,支持您检查和分析 SPICE 模型库,比较不同的模型,以及全面和高效地生成质量检验(QA)报告。经过 10 多年的发展,MQA 已经成为 SPICE 模型验收和签核的行业标准,在领先的集成器件制造商(IDM)、代工厂和设计公司中得到广泛采用。

MQA 的关键优势
– 完全自动化的模型质量检验和报告流程,帮助您提高效率
– 通过定制的知识型检查例程,让您轻松识别模型问题
– 确保您的 EDA 环境在各个代工厂、技术、制程节点和仿真器之间保持一致性
MQA 2017 添加了新的内部 SPICE3 仿真器,用于快速仿真和快速模型质量检验(QA)。支持 Python 脚本,可以自动生成定制的 Excel 表格。新版本支持 Spectre 本地老化仿真和最新的 SmartSpice 版本。检查功能和规则获得了更新,可以支持高级阱邻近效应(WPE)和热噪声质量检验(QA)。MQA 2017 还支持 Microsoft Office 2016 来进行文档编辑和报告。


Keysight Model Quality Assurance (MQA) 2017.2 x64 (模型质量检验)| 775 Mb

Model Quality Assurance (MQA) is an automated SPICE model validation software which allows you to check and analyze SPICE model library, compare different models, and generate quality assurance (QA) reports in a complete and efficient way. With more than ten years of history, MQA has become the industry standard for SPICE model acceptance and signoff and is widely adopted by leading integrated device manufacturers (IDMs), foundries and design houses.

Key Benefits of MQA
– Fully automatic model quality assurance and reporting process to improve the productivity
– Easily to identify the model issues with the customizable knowledge-based checking routines
– Ensure your EDA environment compliance across various foundries, technologies, process nodes and simulators

Language: English
Operating Systems: Windows 7/8.x 64Bit


Keysight Model Quality Assurance (MQA) 2017.2 x64 – 复制到IDM高速下载
http://dl.downloadly.ir/Files/Software2/MQA_2017_Update2_Downloadly.ir.rar

Keysight Genesys 2018 x64

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Keysight Genesys 2018是一款易学易用、经济高效的集成电子设计自动化软件。已经有 5000 位设计人员使用了该软件,并对其给予了很高的评价,这证明它是一项安全的投资。Genesys 在采用的第一年就通过节约的成本让客户收回投资。由于设计人员的需求远远超出射频电路板的应用范围,是德将为购买先进设计系统(ADS)软件的客户提供全款换购,以便进行 MMIC 和多重技术射频系统封装模块设计。Genesys 用户界面包括 6 种常用语言(英语、日语、俄语、韩语,简体中文和繁体中文)版本,因此全球各地的工程师与技术人员都能快速掌握并展开协作。
Genesys 的主要优势
– 最快的系统结构和频率规划工具,以及行业内最全面的射频/微波电路合成功能,可以将手动设计时间由数小时缩短到几分钟。
– 时域和频域电路仿真、优化和统计分析,可实现精确的高性能和高良率设计。
– 快速、高内存使用效率地三维平面电磁场仿真,可确保对射频/微波电路板版图进行彻底的分析,以减少反复调整电路板的次数。


Keysight Genesys 2018 x64 (射频和微波设计)| 1.9 Gb

Genesys is an affordable, accurate, easy-to-use RF and microwave circuit synthesis and simulation tool created for the circuit board and subsystem designer. Automatic circuit synthesis of matching networks, filters, oscillators, mixers, transmission lines, PLL and signal routing structures enable engineers without prior expertise to design these components quickly.

The Genesys synthesis collection is consistently the best selling bundle because no other equivalent capabilities are available in the market at such an affordable price. As a proven safe investment with an installed base of over 5,000 satisfied designers, Genesys literally pays for itself within the first year of deployment by eliminating wasteful hardware iterations through automated circuit synthesis and accurate design.

Key Benefits of Genesys
– Industry’s widest coverage of automated RF & microwave filter, matching and circuit synthesis
– RF system analysis and frequency planning with interactive root-cause problem identification
– Linear and nonlinear RF circuit simulators with optimization and statistical analysis for high-performance and high-yield designs
– 3D-planar EM simulator for analyzing printed circuit board and antenna layout to reduce board turns
– 3X more affordable than competitive products that offer less capablity

Language: English/简体中文/Multilingual
Operating Systems: Windows 7/8.x 64Bit

Cadence Xcelium 18.03 Linux

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Xcelium是首款已通过产品流片的第三代并行仿真平台。基于多核并行运算技术,Xcelium 可以显著缩短片上系统(SoC)面市时间。较Cadence上一代仿真平台,Xcelium单核版本性能平均可提高2倍,多核版本性能平均可提高5倍以上。Cadence Xcelium仿真平台已经在移动、图像、服务器、消费电子、物联网(IoT)和汽车等多个领域的早期用户中得到了成功应用,并通过产品流片验证。如需了解更多内容,请参考。

Xcelium仿真平台具备以下优势,可以大幅加速系统开发:
– 多核仿真,优化运行时间,加快项目进度:第三代Xcelium仿真平台源于收购Rocketick公司带来的技术,是业内唯一正式发布的基于产品流片的并行仿真平台。利用Xcelium可显著缩短执行时间,在寄存器传输级(RTL)仿真可平均提速3倍,门级仿真可提高5倍,DFT仿真可提高 10倍,节约项目时间达数周至数月。
– 应用广泛:Xcelium仿真平台支持多种最新设计风格和IEEE标准,使工程师无需重新编码即可提升性能。
– 使用方便:Xcelium仿真平台的编译流程将设计与验证测试环境代码分配至最优引擎,并自动选取最优CPU内核数目,提高执行速度。
– 采用多项专利技术提高生产力(申请中):优化整个SoC验证时间的新技术包括:为达到快速验证收敛的SystemVerilog Testbench覆盖率和多核并行编译。
 全新Xcelium仿真平台是Cadence验证套件家族的新成员,继承Cadence的创新传统,并全面符合Cadence系统设计实现(SDE)战略,该战略的宗旨是帮助系统和半导体设计公司有效的开发更完整、更具竞争力的终端产品。该验证套件(Cadence Verification Suite)包含最先进的核心引擎技术,采用多种验证架构技术及解决方案,帮助客户优化设计质量,提高生产力,满足不同应用和垂直领域的验证需求。


Cadence Xcelium Parallel Logic Simulation(Xcelium) 18.03 Linux (仿真平台)| 7.5 Gb

Cadence Xcelium Parallel Logic Simulation is the EDA industry’s first production-ready third-generation simulator. It is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster than current solutions. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation simulators. The Xcelium simulator is cloud-ready and runs on your existing compute resources with leading runtime and capacity, making it the simulator of choice throughout the verification flow.

Language: English
Operating Systems: RHEL 5.x