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Tensilica Xtensa Xplorer 7.0.9 Linux

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Cadence Xtensa Xplorer是Tensilica Xtensa处理器的集成开发环境。Xtensa Xplorer允许芯片架构师通过快速描述其处理器所需的关键指令,存储器和外设接口功能,快速探索替代设计方法。
Xtensa Xplorer软件包包括以下内容:
– Xtensa Xplorer,包括TIE开发,处理器配置和软件开发功能
– Xtensa Tools的当前版本,包括软件开发,建模和TIE开发功能
– Xplorer示例演示了Xtensa处理器的功能,包括用于软件开发的示例Xtensa处理器配置构建


Tensilica Xtensa Xplorer 7.0.9 Linux (集成开发环境)| 1.1 Gb

Cadence Xtensa Xplorer is a integrated Development Environment for Tensilica Xtensa Processors.Xtensa Xplorer allows chip architects rapidly explore alternative design approaches by quickly describing the key instruction, memory, peripheral interface functions required by their processor.
Xtensa Xplorer package includes the following:
– Xtensa Xplorer, including TIE development, processor configuration and software development capabilities
– The current version of Xtensa Tools including software development, modeling and TIE development capabilities
– Xplorer samples that demonstrate features of Xtensa processors, including an example Xtensa processor configuration build for software development

Language: English
Operating Systems: RHEL 5.x-7.x

Cadence INCISIVE 15.20.001 Linux

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Cadence设计系统公司是全球电子设计创新的领导者,它推出了其领先的功能验证平台和方法INCISIVE 15.20。Integrated Metrics Center(IMC)和Incisive Enterprise Manager(vManager)可用
随着所有细分市场中的电子产品变得越来越复杂,开发其底层硬件和软件以及整合双方,电子产品将继续变得更加复杂。早期的软件开发,硬件验证,硬件/软件集成和集成系统验证已成为主要挑战,增加了开发成本,项目进度和风险。
使用Cadence Verification Suite,您可以将系统集成时间缩短高达50%,从而加速知识产权(IP)开发,片上系统(SoC)集成以及并发硬件/软件开发。该验证套件由核心引擎,验证结构技术和跨这些技术的解决方案组成.。
核心引擎包括JasperGold形式验证,RocketSim和Incisive仿真,Palladium®仿真和Protium FPGA原型设计。我们开发了每台发动机,以提供一流的技术。
验证结构技术包括验证IP,Incisive vManager规划和指标,Indago调试解决方案以及Perspec软件驱动的测试。我们开发了这些技术以提供流驱动的多引擎验证环境。
该套件中的解决方案包括最短项目进度的总吞吐量,公制驱动的质量签收,以及以应用为中心的重点,以满足移动,网络和服务器,汽车,消费者和物联网(IoT)产品的需求,航空航天和国防以及其他垂直领域。
我们的Verification Suite技术,流程和解决方案支持广泛的行业标准,可供第三方集成,并由我们的生态系统合作伙伴(包括ARM和许多其他合作伙伴)进一步增强。


Cadence INCISIVE 15.20.001 Linux (模型质量检验)| 13.5 Gb

Cadence Design Systems, Inc., a leader in global electronic design innovation, introduced its leading functional verification platform and methodologies, INCISIVE 15.20.
As electronic products across all market segments become more sophisticated, developing their underlying hardware and software, and integrating the two sides, continues to grow more complex. Early software development, hardware verification, hardware/software integration, and integrated system validation have become primary challenges, increasing development costs, project schedules, and risks.
Using the Cadence Verification Suite, you can reduce system integration time by up to 50%, accelerating intellectual property (IP) development, system-on-chip (SoC) integration, and concurrent hardware/software development. This verification suite is comprised of core engines, verification fabric technologies, and solutions spanning these technologies, as shown in Figure 1.
Core engines include JasperGold formal verification, RocketSim and Incisive simulation, Palladium® emulation, and Protium FPGA prototyping. We developed each engine to provide best-in-class technology.
Verification fabric technologies include Verification IP, Incisive vManager planning and metrics, Indago debug solutions, and Perspec software-driven testing. We developed these technologies to provide a flow-driven multi-engine verification environment.
Solutions in the suite include total throughput for the shortest project schedule, metric-driven signoff for quality, and an application-centric focus to meet the needs of products for mobile, networking and servers, automotive, consumer and the Internet of Things (IoT), aerospace and defense, and other vertical segments.
Our Verification Suite technologies, flows, and solutions support a broad range of industry standards, are open for third-party integration, and are further augmented by our ecosystem partners, including ARM and many others.

Language: English
Operating Systems: RHEL 5.x-7.x

Keysight Model Builder Program (MBP) 2017.2 x64

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Model Builder Program (MBP) 2017 介绍了用于静态随机存取存储器(SRAM)单元的新模型提取套件。自动化模型提取流程针对静态模型和紧凑模型进行了增强,包括 BSIM3v3、BSIM4 和 BSIM-CMG。Script API 获得更新,可以支持更多功能。用户界面(UI)也进行了众多改进。内部 SPICE 引擎支持最新的模型版本:BSIM-CMG 110.0、109.0,BSIM-IMG 102.8、102.7,HiSIM2 2.9.0,HiSIM_HV 2.3.2、2.3.1、2.3.0 和 EKV 302.00。


Keysight Model Builder Program (MBP) 2017.2 x64 (模型质量检验)| 775 Mb

Model Builder Program (MBP) is a one-stop solution that provides both automation and flexibility for high-volume model generation. MBP includes automated extraction packages for industry standard models as well as an open interface for modeling strategy customization. Turnkey solutions are also provided for the advanced statistical and mismatch model extraction, layout proximity effects (LPE) modeling, static random access memory (SRAM) cell modeling, HVMOS modeling, scalable Inductor modeling and corner library generation.

Key Benefits of MBP
– Automated extraction packages and the internal engine to increase modeling productivity.
– Script environment to increase the flexibility for customization.
– User friendly GUI and a rich set of modeling utilities to further increase the working efficiency and improve model quality.

Language: English
Operating Systems: Windows 7/8.x 64Bit


Keysight Model Builder Program (MBP) 2017.2 x64 – 复制到IDM高速下载
http://dl.downloadly.ir/Files/Software2/MBP_2017_Update2_x64_Downloadly.ir.rar

Keysight Model Quality Assurance (MQA) 2017.2 x64

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Model Quality Assurance(MQA)是一款自动化的 SPICE 模型验证软件,支持您检查和分析 SPICE 模型库,比较不同的模型,以及全面和高效地生成质量检验(QA)报告。经过 10 多年的发展,MQA 已经成为 SPICE 模型验收和签核的行业标准,在领先的集成器件制造商(IDM)、代工厂和设计公司中得到广泛采用。

MQA 的关键优势
– 完全自动化的模型质量检验和报告流程,帮助您提高效率
– 通过定制的知识型检查例程,让您轻松识别模型问题
– 确保您的 EDA 环境在各个代工厂、技术、制程节点和仿真器之间保持一致性
MQA 2017 添加了新的内部 SPICE3 仿真器,用于快速仿真和快速模型质量检验(QA)。支持 Python 脚本,可以自动生成定制的 Excel 表格。新版本支持 Spectre 本地老化仿真和最新的 SmartSpice 版本。检查功能和规则获得了更新,可以支持高级阱邻近效应(WPE)和热噪声质量检验(QA)。MQA 2017 还支持 Microsoft Office 2016 来进行文档编辑和报告。


Keysight Model Quality Assurance (MQA) 2017.2 x64 (模型质量检验)| 775 Mb

Model Quality Assurance (MQA) is an automated SPICE model validation software which allows you to check and analyze SPICE model library, compare different models, and generate quality assurance (QA) reports in a complete and efficient way. With more than ten years of history, MQA has become the industry standard for SPICE model acceptance and signoff and is widely adopted by leading integrated device manufacturers (IDMs), foundries and design houses.

Key Benefits of MQA
– Fully automatic model quality assurance and reporting process to improve the productivity
– Easily to identify the model issues with the customizable knowledge-based checking routines
– Ensure your EDA environment compliance across various foundries, technologies, process nodes and simulators

Language: English
Operating Systems: Windows 7/8.x 64Bit


Keysight Model Quality Assurance (MQA) 2017.2 x64 – 复制到IDM高速下载
http://dl.downloadly.ir/Files/Software2/MQA_2017_Update2_Downloadly.ir.rar

Keysight Genesys 2018 x64

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Keysight Genesys 2018是一款易学易用、经济高效的集成电子设计自动化软件。已经有 5000 位设计人员使用了该软件,并对其给予了很高的评价,这证明它是一项安全的投资。Genesys 在采用的第一年就通过节约的成本让客户收回投资。由于设计人员的需求远远超出射频电路板的应用范围,是德将为购买先进设计系统(ADS)软件的客户提供全款换购,以便进行 MMIC 和多重技术射频系统封装模块设计。Genesys 用户界面包括 6 种常用语言(英语、日语、俄语、韩语,简体中文和繁体中文)版本,因此全球各地的工程师与技术人员都能快速掌握并展开协作。
Genesys 的主要优势
– 最快的系统结构和频率规划工具,以及行业内最全面的射频/微波电路合成功能,可以将手动设计时间由数小时缩短到几分钟。
– 时域和频域电路仿真、优化和统计分析,可实现精确的高性能和高良率设计。
– 快速、高内存使用效率地三维平面电磁场仿真,可确保对射频/微波电路板版图进行彻底的分析,以减少反复调整电路板的次数。


Keysight Genesys 2018 x64 (射频和微波设计)| 1.9 Gb

Genesys is an affordable, accurate, easy-to-use RF and microwave circuit synthesis and simulation tool created for the circuit board and subsystem designer. Automatic circuit synthesis of matching networks, filters, oscillators, mixers, transmission lines, PLL and signal routing structures enable engineers without prior expertise to design these components quickly.

The Genesys synthesis collection is consistently the best selling bundle because no other equivalent capabilities are available in the market at such an affordable price. As a proven safe investment with an installed base of over 5,000 satisfied designers, Genesys literally pays for itself within the first year of deployment by eliminating wasteful hardware iterations through automated circuit synthesis and accurate design.

Key Benefits of Genesys
– Industry’s widest coverage of automated RF & microwave filter, matching and circuit synthesis
– RF system analysis and frequency planning with interactive root-cause problem identification
– Linear and nonlinear RF circuit simulators with optimization and statistical analysis for high-performance and high-yield designs
– 3D-planar EM simulator for analyzing printed circuit board and antenna layout to reduce board turns
– 3X more affordable than competitive products that offer less capablity

Language: English/简体中文/Multilingual
Operating Systems: Windows 7/8.x 64Bit

Advanced Design System (ADS) 2017.1 x64

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Advanced Design System(ADS)是领先的电子设计自动化软件,适用于射频、微波和信号完整性应用。ADS 是获得商业成功的创新技术(例如 X 参数*和 3D 电磁仿真器)的代表,这些技术已被无线通信与网络以及航空航天与国防领域中的领先厂商广泛采用。对于 WiMAX™、LTE、多千兆位/秒数据链路、雷达和卫星应用,ADS 能够借助集成平台中的无线库以及电路系统和电磁协同仿真功能提供基于标准的全面设计和验证。

ADS 的主要优势
快速、精确、简单易用的全套集成系统、电路和电磁仿真器,能够一次性成功完成桌面流程设计。
特定应用设计指南将长期积累的专业知识应用于简单易用的界面中。

ADS 2017 为充满挑战的无线通信设计提供了 3D 解决方案和更多解决方案,其中包括:

  • 3D 版图查看、路由选择和编辑
  • 多技术 3D 电热仿真
  • 利用 Python 数据链路进行 3D 数据可视化
  • 使用 FEM 进行更强大的 3D 电磁仿真
  • 3D Via Designer:支持访问精确的过孔模型
  • 自动建立线圈等器件的 PCell 结构
  • 用于分层管理的新选件
  • 改善的互操作性
  • SOA 支持更好的可靠性
  • 增强的电路仿真性能

ADS 2017 为信号完整性(SI)和电源完整性(PI)设计所提供的最新特性和功能包括:

  • PIPro——为供电网络提供直流电热仿真
  • PIPro——提供为去耦合电容器和电感器优化的材料清单
  • 3D Via Designer:支持访问精确的参数化差分过孔模型
  • 提高了 IBIS 模型可用性,并提供最新的 IBIS 封装模型组件
  • 极大提升瞬态和通道仿真速度,以便加速批量仿真和高端口数 S 参数测量
  • 统计通道仿真(Sim)更新,以支持 PAM4 IBIS-AMI 模型
  • 在表格视图中进行基片编辑

Advanced Design System (ADS) 2017.1 x64 (电子设计自动化) | 2.0 Gb

Keysight Technologies Inc. pleased to announce the release of Advanced Design System (ADS) 2017. This release introduces a host of new 3D capabilities and enhanced performance in the areas of circuit, electromagnetic (EM), and electro-thermal simulation, all packed into a single simulation platform.
Advanced Design System 2017 Release Notes:
Feature Updates

Simulation
– Signal Integrity/Power Integrity
– Silicon RFIC Interoperability
– EM Simulation
– FEM Performance and Parallel Simulation
– EM Usability (EM for Everyone)
– Circuit Simulation Performance
– Electro-Thermal
– Dynamic Link
Design Environment
– Layout and Schematic Editing
– Technology and Substrates
– 3D Layout Design
– 3D Viewing, Routing and Editing
– 3D FEM Simulation Performance
– 3D Data Visualization
– 3D Electro-Thermal Simulation
– Printing
Verification and Manufacturing Artwork
– Layout Versus Schematic (LVS)
– Design Rule Checker (DRC)
– Assura DRC Link
– Artwork Translators
– PCB Links
Design Enablers
– CoilSys
– Encrypted iRCX support
– Data Flow
– Examples
– PDKs
General Enhancements
– Licensing amd Installation
– Ultra High Resolution Screen
– Quick Start and Getting Started
– ADS Exports from BenchVue

Language: English
Operating Systems: Windows 7/8.x 64Bit

Cadence Xcelium 18.03 Linux

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Xcelium是首款已通过产品流片的第三代并行仿真平台。基于多核并行运算技术,Xcelium 可以显著缩短片上系统(SoC)面市时间。较Cadence上一代仿真平台,Xcelium单核版本性能平均可提高2倍,多核版本性能平均可提高5倍以上。Cadence Xcelium仿真平台已经在移动、图像、服务器、消费电子、物联网(IoT)和汽车等多个领域的早期用户中得到了成功应用,并通过产品流片验证。如需了解更多内容,请参考。

Xcelium仿真平台具备以下优势,可以大幅加速系统开发:
– 多核仿真,优化运行时间,加快项目进度:第三代Xcelium仿真平台源于收购Rocketick公司带来的技术,是业内唯一正式发布的基于产品流片的并行仿真平台。利用Xcelium可显著缩短执行时间,在寄存器传输级(RTL)仿真可平均提速3倍,门级仿真可提高5倍,DFT仿真可提高 10倍,节约项目时间达数周至数月。
– 应用广泛:Xcelium仿真平台支持多种最新设计风格和IEEE标准,使工程师无需重新编码即可提升性能。
– 使用方便:Xcelium仿真平台的编译流程将设计与验证测试环境代码分配至最优引擎,并自动选取最优CPU内核数目,提高执行速度。
– 采用多项专利技术提高生产力(申请中):优化整个SoC验证时间的新技术包括:为达到快速验证收敛的SystemVerilog Testbench覆盖率和多核并行编译。
 全新Xcelium仿真平台是Cadence验证套件家族的新成员,继承Cadence的创新传统,并全面符合Cadence系统设计实现(SDE)战略,该战略的宗旨是帮助系统和半导体设计公司有效的开发更完整、更具竞争力的终端产品。该验证套件(Cadence Verification Suite)包含最先进的核心引擎技术,采用多种验证架构技术及解决方案,帮助客户优化设计质量,提高生产力,满足不同应用和垂直领域的验证需求。


Cadence Xcelium Parallel Logic Simulation(Xcelium) 18.03 Linux (仿真平台)| 7.5 Gb

Cadence Xcelium Parallel Logic Simulation is the EDA industry’s first production-ready third-generation simulator. It is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster than current solutions. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation simulators. The Xcelium simulator is cloud-ready and runs on your existing compute resources with leading runtime and capacity, making it the simulator of choice throughout the verification flow.

Language: English
Operating Systems: RHEL 5.x

Cadence MDV 18.03 Linux

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Cadence vManager Metric-Driven Signoff Platform (MDV)是原来Incisive中的验证规划和管理工具vManager和IMC,现在独立出来单独发行。


Cadence Metric-Driven Verification Signoff (MDV) 18.03 Linux (验证规划和管理工具)| 1.66 Gb

Metric-Driven Signoff is a unique Cadence methodology and technology for measuring and signing off on the design and verification metrics used during the many milestones typical in any integrated circuit (IC) development. While milestones and metrics vary by design type and end application, the final verification signoff will at, a minimum, contain the criteria and metrics within a flexible, human-readable, user-defined organizational structure. Automated data collection, project tracking, dashboards, and in-depth report techniques are mandatory elements to eliminate subjectivity, allowing engineers to spend more time on verification and less time manually collecting and organizing data.

Language: English
Operating Systems: RHEL 5.x

Coventor SEMulator3D 7.0 x64

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Coventor SEMulator3D是一个强大的3D半导体和MEMS工艺建模平台,提供广泛的技术开发能力。 基于高效的物理驱动体素建模技术,SEMulator3D具有模拟完整工艺流程的独特能力。利用SEMulator3D虚拟制造平台,工程团队可以高效地开发工艺流程并在实际制造之前执行自动虚拟实验。
SEMulator3D平台为开发先进半导体制程及MEMS制程提供了一种新的方法。它是业内最快,最强大,最精确的3D半导体工艺建模平台。 SEMulator3D的过程预测能力使所有半导体供应链的参与者受益,从技术开发人员到无厂IP供应商,再到设备和工艺供应商。

优势功能:
– 降低工艺开发成本、减少研发周期
– 上产线前发现工艺问题
– 执行变量实验,实际fab中很难执行
– 技术开发的每一步(leverage)进行虚拟制造
– 多应用案例和应用的灵活平台
– 任何工艺和版图的可应用性,regardless of complexity or technology
– 预测设计与整合工艺之间的复杂交


Coventor SEMulator3D 6.1/7.0 x64 (3D半导体和MEMS工艺建模) | 411.0MB

Coventor SEMulator3D 7.0 – the newest version of its semiconductor virtual fabrication platform. With added features, performance improvements, and a new Device Analysis capability, SEMulator3D 7.0 addresses both process and device simulation while lowering the barriers to advanced semiconductor technology development. The new Device Analysis capability enables seamless understanding of how process changes, process variability, and integration schemes directly impact transistor device performance.

SEMulator3D Device Analysis

The new Device Analysis capability can extract electrical characteristics of a transistor and explore process variability on device operation, all directly within SEMulator3D. Designers can generate transistor IV curves and perform automatic device parameter extraction from those curves. Transistor performance can be measured across changes in patterning, lithography, etch, deposition, and other process integration effects. This add-on functionality provides insight into how process integration decisions, such as patterning schemes and allowed unit process variations, impact transistor device performance.

SEMulator3D 7.0 Productivity Enhancements

The new version of SEMulator3D 7.0, which is available now, includes many additional features and performance enhancements, including:

New Calibration Function

SEMulator3D Analytics now includes a calibration function, which automates calibration of a virtual model against experimental measurements and target specifications, accelerating the generation of predictive, silicon-accurate process models.

New Viewer and Rendering Engine

An all-new rendering engine includes faster loading, interaction, construction and exporting of very large models, along with the ability to generate higher fidelity images, enabling larger models (such as 3D NAND devices) to be built faster and better.

New Netlist Extraction Feature

Using this new feature, users can extract resistance and capacitance information of sub-circuits for use in third-party SPICE simulation environments. This can be used to improve a designer’s understanding of how upstream process variations impact overall electrical circuit performance, such as circuit timing changes caused by fabrication variations.

New 3D Mesh Export Capability

Ability to generate new, high-quality Delaunay meshes, to support robust and accurate modeling of complex 3D structures such as material interfaces and feature edges.

Language: English
Operating Systems: Windows 7/8.x/10.x 64Bit


Keysight IC-CAP 2018 x64

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集成电路表征和分析程序(IC-CAP)2018 是进行直流和射频半导体器件建模的工业标准。IC-CAP 能够从高速/数字、模拟和功率射频应用软件中提取出精确而紧凑的模型。当前,大多数领先的半导体制造商和集成器件制造商(IDM)都是采用 IC-CAP 对芯片 CMOS、Bipolar、混合砷化镓(GaAs)、氮化镓(GaN)以及其他器件技术进行建模。IC-CAP 是一种非常先进的可定制建模软件,其中包括测量、仿真、优化和统计分析等工具。

IC-CAP 的主要优势
– 开放式软件体系结构能够确保优异的测试精度,并支持您非常灵活地生成和自动执行测量、提取和验证程序
– 针对工业标准 CMOS 模型(例如 BSIM3/BSIM4、PSP 和 HiSIM)的成套提取解决方案,可显著缩短学习过程,提高模型精度
– 直接连接到商用仿真器,确保提取的模型与电路设计人员使用的仿真器保持一致性


Keysight IC-CAP 2018 x64 (器件建模)| 1.1 Gb

Integrated Circuit Characterization and Analysis Program (IC-CAP) is the industry standard for DC and RF semiconductor device modeling. IC-CAP extracts accurate compact models used in high speed/digital, analog and power RF applications. Today’s most advanced semiconductor foundries and IDMs rely on IC-CAP for modeling silicon CMOS, Bipolar, compound gallium arsenide (GaAs), gallium nitride (GaN) and many other device technologies. IC-CAP is the most advanced, customizable modeling software and includes measurement, simulation, optimization and statistical analysis tools.

Key Benefits of IC-CAP
– Open software architecture enables maximum accuracy and provides ultimate flexibility to create and automate measurement, extraction and verification procedures
– Turnkey extraction solutions for industry standard CMOS models, such as BSIM3/BSIM4, PSP and HiSIM, minimize the learning curve and maximize model accuracy
– Most direct links to commercial simulators ensure consistency between extracted models and the simulators used by circuit designers

Language: English
Operating Systems: Windows 7/8.x 64Bit