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Integrand EMX With Virtuoso Interface 5.3 Linux64

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Integrand EMX是高频,射频和混合信号集成电路的电磁仿真器。它独特的重点是加之无与伦比的速度和精度完全自动化。 EMX得到了广大客户的基准比一个数量级比业界领先的有限元和边界元工具,更快更多。 EMX是建立在最大的自动化的理念,与业界标准的输入和输出格式,在命令行脚本化饱满,与现代IC布局功能自动处理。需要预先安装Cadence Virtuoso IC 6.1.x Linux。


Integrand EMX With Virtuoso Interface 5.2/5.3 Linux64 (电磁仿真器) | 34.0MB

Integrand EMX is an electromagnetic simulator for high-frequency, RF, and mixed-signal integrated circuits. Our unique emphasis is on complete automation coupled with uncompromised speed and accuracy. EMX has been benchmarked by our customers to be more than an order of magnitude faster than the leading finite-element and boundary element tools in the industry. EMX is built on a philosophy of maximal automation, with industry-standard input and output formats, full scriptability from the command line, and automated handling of modern IC layout features.

Language: English
Operating Systems: RedHat Entrprise Linux 5.x-7.x
System Requirements:Cadence Virtuoso IC 6.1.x Linux


Synopsys SiliconSmart 2017.12 SP2 Linux64

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SiliconSmart ADV是一种综合性标准单元库特性表征和品质保证(QA)解决方案,这种改进型解决方案可以生成PrimeTIme签核品质库,并在可用计算资源上提供最大的吞吐量。SiliconSmart ADV独特的授权许可方法可以轻松地适应不同的工作任务量,从而免去了特性表征团队的负担,使他们无须去预测未来的工作量要求以及在传统的繁琐授权许可方法限制下操作。此外,创新性SiliconSmart技术利用内嵌的黄金参考SPICE引擎,来为生成先进的LibertyTM模型提供特性表征加速,PrimeTIme静态时序分析(STA)使用该模型来准确地解释超低电压FinFET工艺对时序的影响。这包括PrimeTIme参数片上变异(POCV)、先进的波形传播(AWP)和电迁移(EM)分析。
SiliconSmart ADV通过一个同一许可证,提供了最先进标准单元库的库特性表征和品质保证所需的一切东西。为了实现最佳的准确性和最快的吞吐量,SiliconSmart ADV包括内嵌的Synopsys FineSim SPICE和Synopsys HSPICE电路仿真解决方案。它还提供灵活的多核许可来优化大型计算中心环境中的吞吐量,并轻松地适应不断变化的特性表征需求。SiliconSmart ADV综合性的LVF特性表征和建模性能实现了一流的PrimeTIme POCV变异分析。智能LVF性能优化技术提供最高的吞吐量和准确性。为了支持单元层EM特性表征,对最新的Liberty EM模型扩展的支持也被包括了进来。SiliconSmart ADV还提供一套工具加速签核品质库的手工执行及易于出错的品质保证过程。整个库认证过程将自动进行并行化处理,以提供快速的周转时间并尽早确定问题。可视化的辅助措施和智能化组织产生的结果有助于快速隔离问题区域,并提供品质保证管理度量指标。


Synopsys SiliconSmart 2017.12 SP2 Linux64 (ADV单元库特性表征解决方案)| 640 Mb

SiliconSmart is a comprehensive characterization solution for standard cells, I/O, complex cells and memory. It generates accurate model libraries tightly correlated with Synopsys’ digital implementation tools. Its built-in FineSim; simulation technology and tight integration with the gold-standard HSPICE; circuit simulator enable characterization and signoff accuracy. SiliconSmart supports all of the standard models, including NLDM (non-linear delay model), CCS (composite current source) and AOCV (advanced on-chip variation) models.
Benefits

  • SiliconSmart’s precise characterization and modeling capability combined with HSPICE golden accuracy is critical for producing signoff-quality library models, including timing, power, signal integrity and OCV to ensure best PrimeTime accuracy during static timing and power analysis. This unique platform-level integration of SiliconSmart produces the best correlation between PrimeTime and HSPICE for advanced technology nodes

Comprehensive solution

  • SiliconSmart is a comprehensive, unified solution that generates libraries for standard cells, I/Os and complex cells, such as multi-bit flip-flops and memories

High performance with pre-characterization optimization

  • SiliconSmart increases performance by using innovative pre-characterization optimization and intelligent optimization techniques that reduce the number of simulation runs required during the library characterization phase

Advanced node-ready

  • SiliconSmart is ready for characterizing and modeling libraries at advanced technology nodes, such as 16-nm and 14-nm. It supports generation of POCV coefficients and supports the latest FinFET models

Language: English
Operating Systems:RHEL 5.x-7.x 64Bit

Synopsys Custom WaveView/CustomExplorer 2017.12 SP2

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Custom WaveView 是一个针对模拟和混合信号 IC 的图形化波形观测仪和仿真后处理工具。Custom WaveView 的功能包括快速加载、显示滚动、大型波形文件的缩放、多种仿真器格式支持及一系列丰富的模拟和混合信号分析功能。
优势

  • 高性能的波形数据库 I/O,可快速访问大量仿真数据
  • 广泛的混合信号显示功能和分析功能,可从仿真结果中提取测量值
  • 可用于多个仿真器的单个波形工具
  • 嵌入式 HSPICE .MEASURE 指令支持和 .ALTER 仿真器的参数绘图
  • 瞬态、AC、RF、混合信息显示和分析
  • 用于编程复杂用户后处理脚本的可选 Tcl API
  • 灵活的波形分组 – 从同一个电路排线表或不同电路排线表上运行的不同仿真器中增加多个波形视图

Synopsys Custom WaveView/CustomExplorer 2017.12 SP2 Win/Linux64 (图形波形查看及后处理)| 120 Mb

Custom WaveView is a graphical waveform viewer and simulation post-processing tool for analog and mixed-signal ICs. Custom WaveView features fast loading, display scrolling, and zooming of very large waveform files, multiple simulator format support, and a rich set of analog and mixed-signal analysis features.
Benefits

  • High-performance waveform database I/O to quickly access large amounts of simulation data
  • Extensive mixed-signal display functions and analysis capabilities to extract measurements from simulation results
  • Single waveform tool for multiple simulators
  • Built-in support for HSPICE .MEASURE command and parametric plots for .ALTER simulations
  • Transient, AC, RF, mixed-signal display and analysis
  • Optional Tcl API for programming complex user post-processing scripts
  • Flexible waveform grouping—add multiple waveform views, either from different simulator runs on the same circuit netlist or from different netlists

Language: English
Operating Systems: Windows 7/8.x 64Bit/RHEL 5.x-7.x

Synopsys SpyGlass 2017.12 SP2 Linux64

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SpyGlass平台针对VERILOG和VHDL用先进的静态和动态分析来检查和诊断设计中可能存在的潜在问题,然后用其分析和追踪引擎来追踪问题的根源,最后给出一个解决问题的方法和建议。SpyGlass能够指出SOC问题中的非常复杂的问题,例如跨时钟域问题、同步问题以及SOC设计中的集成问题。并且,SpyGlass还可以检查电子设计规则(ERC)来确保设计符合工业设计标准或者用户自己定义的标准。

SpyGlass还提供了四个功能强大的选项:
(一)SpyGlass CDC提供了业界最完整的多时钟域解决方案,能自动识别各种同步手段(包括HandShake,FIFO),能采用Formal引擎验证同步方法在功能上的正确性。
(二)SpyGlass Constraints帮助设计人员在设计的整个流程中生成,验证和管理他们的约束文件。
(三)SpyGlass DFT提供了能够预测ATPG的测试覆盖率分析的能力,基于这个选项,用户可以很容易地预计所作设计的可测试性并且利用工具提供的指导来提高设计的可测试性。
(四)SpyGlass LowPower能够让用户能够快速分析出设计中的功耗效率问题,从而在还没有达到后端工序的情况下快速地进行功耗的优化,在power estimate工具中,用户甚至可以在不进行逻辑综合和物理实现的情况下对功耗进行量化的计算。


Synopsys SpyGlass 2017.12 SP2 Linux64 (Verilog检查工具)| 640 Mb

SpyGlass use many advanced algorithms and analysis techniques, provides designers with insight about their design, early in the process at RTL. It functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.
Spyglass is an important platform of Synopsys RTL verification solution that provides complete static analysis to ensure all aspects of the design are optimized before implementation such as Lint, CDC, Power, Constraints, DFT/DSM etc.

Language: English
Operating Systems: RHEL 5.x-7.x 64Bit

Synopsys Custom Compiler 2017.12-SP1 Linux64

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Custom Compiler将定制设计任务时间由数天缩短至数小时,消弭了FinFET的生产力差距。为了将FinFET版图生产力提升到新的高度,Synopsys采用了新颖的定制设计方法,即开发视觉辅助自动化技术,从而提高普通设计任务的速度,降低迭代次数并支持复用。通过与行业领先的客户的密切合作,Custom Compiler已经在最先进的节点上进行生产工作,并通过行业领先的工厂获得了FinFET工艺技术的支持(参看今天新闻辅稿)。许多Custom Compiler用户将于今天在圣塔克拉拉会议中心开幕的硅谷Synopsys用户群大会上分享各自的经验。

视觉辅助自动化

Custom Compiler Assistants可提高生产力,它利用版图设计人员所熟悉的图形使用模式,无需编写复杂代码和约束条件,无需额外设置,Custom Compiler即可自动处理日常和重复性工作。Custom Compiler提供了四种辅助功能:Layout、In-Design、Template和Co-Design。

· Layout Assistants通过可视觉引导的自动布局及绕线提高了设计速度。该款绕线器是连接FinFET阵列和大型M型晶体管的首选。它可以自动克隆连接并创建 pin tap。用户仅使用鼠标就可引导绕线器,由Custom Compiler自动完成绕线细节。设计人员可以使用创新方法进行器件布局。该方法允许用户持续优化,在提供布局选择的同时使版图设计人员能够完全控制结果,无需预先输入任何文本约束条件。

· In-Design Assistants通过在验收验证前捕捉物理和电气错误,降低成本高昂的设计迭代次数。Custom Compiler包括速度极快并始终保持激活状态的嵌入式设计规则检查(DRC)引擎。另外,Custom Compiler还内建电迁移检查以及电阻和电容提取引擎。与其他“电感知”工具不同,Custom Compiler的提取功能基于Synopsys黄金标准的StarRC™内核。

· Template Assistants帮助设计人员复用现有知识累积,使之轻松将之前的版图决策用于新的设计。Template Assistants实际上可以通过Layout Assistants的布局器和绕线器从已完成的工作中自动学习知识。Template Assistants智能识别与先前完成的电路类似的电路,并支持用户将相同的版图和绕线模式当作模板用于新的电路。Custom Compiler出厂时加载了一套内置常用电路模板,如电流镜、电平位移器和差分对。

· Co-Design Assistants将IC Compiler™和Custom Compiler合并为统一的定制和数字实现解决方案。用户可以自由地在Custom Compiler与 IC Compiler之间来回切换,使用各自的指令持续完成自己的设计。利用Co-Design Assistants,IC Compiler用户可以在任何实现阶段对其数字设计执行全定制编辑。同样地,Custom Compiler用户可以利用IC Compiler在自己的定制设计中实施数字实现流程。Co-Design Assistants的无损多次往返功能可确保跨所有数字和定制数据库同步所有变更。

Custom Compiler基于行业标准Open Access数据库,提供包括电路图、模拟分析与版图的开放环境。Custom Compiler结合Synopsys的电路仿真、物理验证以及数字实施工具,提供了一种全面的定制设计解决方案。


Synopsys Custom Compiler 2017.12-SP1 Linux64 (定制设计解决方案)| 2.757 Gb

Custom Compiler is Synopsys’ full-custom solution that features the pioneering visually-assisted automation flow that speeds up custom design tasks, reduces iterations and enables reuse. Tuned for rapid implementation of FinFET custom designs, it shortens the time it takes to complete FinFET custom design tasks from days to hours. Its visually-assisted automation flow leverages the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.

Highlights
– Template Assistants help designers reuse existing custom layout know-how
– In-Design Assistants reduce iterations with native design rule checks and parasitic extraction
– Layout Assistants speed up layout tasks with user-guided placement and routing
– Co-Design Assistants unify custom and digital flow to accelerate mixed-signal IC design

Language: English
Operating Systems: RHEL 5.x-7.x 64Bit

Synopsys Hspice 2017.12 Win/Linux

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Synopsys Hspice采用了最精确的、经过验证的集成电路器件模型库和先进的仿真和分析算法,提供了一个高精度的电路仿真环境。 随着集成电路的几何尺寸不断变小,对高精度电路仿真器的需求也更加迫切。现在的设计者需要一个可以精确预测IC设计的时序、功耗和功能的高精度仿真器。HSPICE为业界提供了最可信任的仿真器引擎和大量的器件模型。HSPICE模拟器引擎已经成功的应用于超过一百万个的设计中。HSPICE先进的电路模拟算法使得其收敛性大大优于其他工具。
● 为电路模拟提供了最高的精度
● 支持最精确、最广泛的业界标准和知识产权仿真模型
● 为广大芯片生产厂商、用户所支持,符合业界标准格式,所以HPSICE被易于采用
● 包括了大量的互联和信号完整性分析
● 支持大量单元特性的功能
● 提供对电路优化、对设计进行测定分析的功能


Synopsys Hspice 2017.12 Win/Linux (高精度电路仿真环境) | 441 Mb

Synopsys Hspice is the industry s gold standard for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With over 25 years of successful design tapeouts, HSPICE is the industry s most trusted and comprehensive circuit simulator.
Design Challenges
As IC geometries continue to shrink, the need for an accurate circuit simulator is critical. Designers require a highly accurate circuit simulator to precisely predict the timing, power consumption, functionality, and yield of their designs. As board and package speeds increase, designers need to employ increasingly accurate signal integrity analysis.

Accuracy
Gold standard for accurate circuit simulation.
Extensive model support of the most accurate and expansive set of industry-standard and proprietary simulation models.
Performance
HSPICE Just Got Faster Again! Synopsys has made HSPICE a performance leader.
Run post-layout simulations up to 3X faster on 1 core processors and up to 6X faster on 4 core processors with 2008.03 HSPICE
Significant speed up for cell characterization applications, large extracted netlists, signal integrity, and 65 nm designs.
Design for Yield – Process Variability and Device Reliability Simulation
Process & Interconnect Variation ?Models both device and interconnect variation
Variation Block – powerful and flexible mechanism for defining process variation effects.
AC & DCMatch – efficient statistical simulation for local parameter mismatch effects.
Smart Monte Carlo – all-purpose statistical simulation that runs several times faster than tradition Monte Carlo techniques.
MOSRA device reliability analysis ?simulate HCI and NBTI device aging effects
Board and Package Design Integrity Analysis
Enhanced W-elements and S-parameters to model signal integrity issues and support SI Analysis.
Support for massive 500 port S-parameters
RF and High Speed Simulation
Best RF Simulator for PLL and VCO applications
Most Accurate RF Simulator
Fastest RF Simulator
High Capacity RF Simulator, 10000+ transistors with both Harmonic Balance and Shooting Newton algorithms
Comprehensive solution simulates low noise amplifiers, power amplifiers, filters, AGC circuits, oscillators, mixers, multipliers, modulators, demodulators, and VCOs.

Language: English
Operating Systems: Windows 7/8.x/10.x/RHEL 6.6+, 7.x/SLES 11.x and 12.x x64

Synopsys Synplify FPGA 2018.03 SP1 Win/Linux

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Synplify FPGA包含可选Synplify Pro和Synplify Premier FPGA综合工具。
Synopsys Synplify FPGA设计软件提供了一个高品质,高性能和易于使用的FPGA实现和调试环境。采用Synopsys的FPGA工具套件增益设计师快速进入超结果为复杂的FPGA,面积优化成本和降低功耗,自动化软错误缓解,分层设计能力和多FPGA厂商的支持。该的Synplify Pro和Synplify Premier FPGA设计工具,通过提供链接到高性能功能验证与VCS仿真和集成Synphony模型编译器的信号处理硬件的高层次综合提供额外的价值。
许多设计和验证团队越来越倾向于使用基于 FPGA 的原型验证,以便使产品及时进入市场。 基于 FPGA 的 Synopsys 原型验证解决方案可以使开发者尽早进行芯片制造前的嵌入式软件开发和软硬件协同设计,从而缩短上市时间并降低昂贵的器件改版费用。 同时,我们紧密集成且易于使用的HAPS硬件和软件工具套件可大幅加快从单个 IP 模块到处理器子系统再到整个SoC的软件开发、软硬件集成和系统验证。


Synopsys Synplify FPGA 2017.09/2018.03 SP1 Win/Linux (FPGA综合工具) | 1097 Mb

点击放大完整功能测试图片

Synplify Premier solution is the industry’s most productive FPGA implementation and debug environment. It includes all the features of Synplify Pro and additionally provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes.
The Synplify Premier software delivers fast turnaround time capabilities and feedback for users seeking to quickly implement the design on the board or to tune their design projects prior to final implementation. It addresses the most challenging aspects of FPGA design including timing closure and has the ability to perform graph-based physical synthesis for more accurate upfront timing prediction. It provides flows for fast logic verification and RT-Level debug. Under the hood, it contains optimization techniques that enhance DSP, IP and embedded design results. For ASIC prototypers, it delivers ASIC design file and DesignWare compatibility as well as tight integration with the Confirma Rapid Prototyping platform and FPGA vendor back-end tools as well as vendor embedded tools including Altera SoPC Builder and Xilinx EDK.
The Synplify Premier product offers FPGA Designers and ASIC Prototypers, targeting single FPGA-based prototypes, with the most efficient method of design implementation and debug. The Synplify Premier software provides in-system verification of FPGAs, dramatically accelerates the debug process, and provides a rapid and incremental method for finding elusive design problems.
The Synplify Premier software advantages include:
* technology and vendor independence
* in-system debug
* fast timing closure
* RTL analysis
* DSP-friendly synthesis algorithms
* superior Quality of Results (QoR)

Language: English
Operating Systems: Windows 7/8.x/10.x/RHEL 6.6+, 7.x/SLES 11.x and 12.x

NI AWR Design Environment with Analyst 14.0.9138 x64

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NI AWR Design Environment v14在设计流程管理和仿真中引入了许多创新,支持单片微波集成电路(MMIC),RFIC,多芯片模块和印刷电路板(PCB)技术。 模拟功能已在Microwave Office APLAC谐波平衡(HB)和Visual System Simulator(VSS)系统级仿真引擎中得到扩展,并且AXIEM平面3D和Analyst任意3D电磁(EM)解算器 。
多芯片模块的设计自动化和仿真已得到增强,在单个项目中更多地支持多技术工艺设计套件(PDK),对OpenAccess(原理图)数据库的新支持以及对Spectre RFIC网络表的APLAC协同仿真支持,以及简化的EM布局和端口创建。对于PCB设计,新的导入向导支持ODB ++和IPC2851数据库,以提供与主流第三方PCB布局工具的互操作性。还增加了新的布局编辑功能,以及简化的多技术管理。此外,V14中的新型EM Socket II架构为来自ANSYS,CST和Sonnet的AWR连接合作伙伴解决方案提供了改进的第三方EM仿真流程,使设计人员能够访问NI AWR设计环境中的备用EM仿真器
V14通过用于5G候选调制波形和相控阵行为模型增强的新通信库提供的高度精确的模拟RF前端组件测量来满足特定的系统要求。 RF功率放大器设计人员现在可以使用VSS中的系统级负载拉动分析为通信性能度量(如邻道功率比(ACPR)和误差矢量幅度(EVM))生成轮廓。 RF滤波器设计人员可以利用iFilter综合工具中的新功能加速其产品开发,并且被动和控制组件(如变压器,耦合器和混频器)的设计人员可以从新的综合功能和强大的新的优化方法中受益,使用专有的遗传算法更坚固的设计。


NI AWR Design Environment with Analyst 14.0_9067 x64 (高频电路和微波系统设计)| 321 Mb


NI AWR Design Environment v14 introduces numerous innovations in design flow management and simulation, supporting monolithic microwave integrated circuit (MMIC), RFIC, multi-chip module and printed circuit board (PCB) technologies. Simulation capabilities have been expanded within the Microwave Office APLAC harmonic balance (HB) and Visual System Simulator (VSS) system-level simulation engines and speed improvements have been made to both its AXIEM planar 3D and Analyst arbitrary 3D electromagnetic (EM) solvers.
Design automation and simulation have been enhanced for multi-chip modules, with greater support for multi-technology process design kits (PDKs) within a single project, new support for OpenAccess (schematic) databases and APLAC co-simulation support for Spectre RFIC netlists, as well as simplified EM layout and port creation. For PCB design, a new import wizard supports ODB++ and IPC2851 databases to provide interoperability with mainstream third-party PCB layout tools. New layout editing capabilities have also been added, along with simplified multi-technology management. Furthermore, the new EM Socket II architecture within V13 offers improved third-party EM simulation flows for AWR Connected partner solutions from ANSYS, CST and Sonnet, giving designers access to alternate EM simulators within NI AWR Design Environment.
V14 addresses specific system requirements with highly accurate simulated RF front-end component measurements provided through new communication libraries for 5G candidate modulation waveforms and phased-array behavioral model enhancements. RF power amplifier designers can now use the system-level load-pull analysis in VSS to generate contours for communication performance metrics such as adjacent channel power ratio (ACPR) and error vector magnitude (EVM). RF filter designers can take advantage of new capabilities in the iFilter synthesis tool to accelerate their product development and designers of passive and control components such as transformers, couplers and mixers can benefit from the new synthesis capabilities and powerful new optimization methods using proprietary genetic algorithms for more robust designs.

Language: English
Operating Systems: Windows 7/8.x/10 64Bit


Download Link (IDM下载)
NI AWR Design Environment 13.02

Mentor Graphics Tanner Tools With HyperPX 2016.2 x64

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Tanner EDA Tools是一款功能强大的集成电路设计软件,主要功能包括数模混合电路、模拟电路和MEMS设计等,在电路设计、版图设计和仿真验证方面带来了很大的帮助,可以满足专业人员的需求。目前版本是Tanner EDA Tools 2016.2 Update1.

软件特点
– 完整的模拟/数模混合IC全定制设计组件
– OpenAccess,LEF/DEF,Liberty和SDF数据格式支持
– 支持多重抽象级网表仿真:行为级、模块级、门级
– 调试和验证支持System Verilog, Verilog, Verilog-AMS, Verilog-A和VHDL等语言
– 提供内建的库导航器,有效跨越自顶向下和自底向上的层次化设计查看单元视图
– 自顶向下的混合信号仿真
– 已验证的,与综合兼容的DFT支持
– 高速时序分析
– 全角度版图编辑
– 实时DRC检查,DRC和LVS验证与Calibre工具兼容
– 使用SDL加速版图设计,可进行自动布局布线,支持HSPICE, PSPICE, Verilog和CDL等格式数据导入
– 支持参数化cell,称为T-cell,可用于可编程接口操作(UPI),创建自动化宏
– HiPer DevGen可实现参数化器件生成版图
– 支持多Foundry工艺
– 提供多语言菜单(英语,日语,简体中文、繁体中文,德语,意大利语和俄语等)


Tanner Tools 2016.2 Update1 With HyperPX x64 (集成电路设计)| 546 Mb

Mentor Tanner Tools 2016.2 provides electronic design automation (EDA) software used by companies in a wide variety of industries. Its solutions enable designers to move rapidly from concept to silicon by enabling the design, layout, and verification of analog/mixed-signal ICs, ASICs, and MEMS.
Tanner EDA solutions offer designers the perfect combination of price and performance to meet any design challenge. The company’s solutions include tools for:

  • Schematic Capture: S-Edit
  • Simulation: T-Spice, W-Edit
  • Physical Layout: L-Edit
  • Verification: HiPer Verify, L-Edit Standard DRC, L-Edit LVS and more
  • Parasitic Layout Extraction: HiPer PX, 2D and 3D parasitic layout extraction

These scalable solutions have a range of applications in the biomedical, consumer electronics, next-generation wireless, imaging, power management, and RF market segments.

Language: English/简体中文/Multilingual
Operating Systems: Windows 7/8.x 64Bit

Aldec Riviera-PRO 2018.02 x64/Linux64

Publisher阅读(387)

Aldec Riviera的混合语言VHDL、Verilog和SystemVerilog HDL编译器与C/C++编译器内核的直接连接,提供了无缝的SystemC协同仿真环境,这种连接以前只能通过慢速的PLI/VPI等接口通信实现。Riviera 允许工程人员通过设计与验证工具建立SystemC模块,并采用外部C编译器进行编译和协同仿真,仿真结果可在Riviera的Waveform Viewer/Editor中进行检验。 除协同仿真外,SystemC还为配合SystemC验证库(SCV)使用的处理级(transaction-level)测试平台开发提供了条件,设计人员通过SystemC可在短期内创建更可靠的测试平台,其处理级的执行速度比事件驱动的测试平台快100倍以上。
Riviera为系统级验证工程人员提供了几个采用HDL的SystemC设计样例。由于多数系统设计人员比较熟悉C++,SystemC为传统硬件工程师与系统工程师之间建立了快速沟通。然而,如果缺乏必要的培训,多数工程人员对其还难以掌握。
由于Riviera将C++中的面向硬件的结构以一个标准C++类库的形式提供,支持SystemC为用户提供了很大便利,该软件利用软硬件操作的概念实现了大跨度的设计和验证。SystemC提供了一个可互操作建模的平台,能实现快速的系统级C++模型开发与交换,此外还为系统级工具的开发提供了一个稳定的平台。


Aldec Riviera-PRO 2018.02 Win/Linux x64 | 298 Mb

Aldec Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

Language: English
Operating Systems: Windows 7/8.x/10.x/RHEL 5.x-7.x 64Bit