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Keysight Model Quality Assurance (MQA) 2019 x64

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Model Quality Assurance(MQA)是一款自动化的 SPICE 模型验证软件,支持您检查和分析 SPICE 模型库,比较不同的模型,以及全面和高效地生成质量检验(QA)报告。经过 10 多年的发展,MQA 已经成为 SPICE 模型验收和签核的行业标准,在领先的集成器件制造商(IDM)、代工厂和设计公司中得到广泛采用。

MQA 的关键优势
– 完全自动化的模型质量检验和报告流程,帮助您提高效率
– 通过定制的知识型检查例程,让您轻松识别模型问题
– 确保您的 EDA 环境在各个代工厂、技术、制程节点和仿真器之间保持一致性
MQA 2017 添加了新的内部 SPICE3 仿真器,用于快速仿真和快速模型质量检验(QA)。支持 Python 脚本,可以自动生成定制的 Excel 表格。新版本支持 Spectre 本地老化仿真和最新的 SmartSpice 版本。检查功能和规则获得了更新,可以支持高级阱邻近效应(WPE)和热噪声质量检验(QA)。MQA 2017 还支持 Microsoft Office 2016 来进行文档编辑和报告。


Keysight Model Quality Assurance (MQA) 2019/2017.2 x64 (模型质量检验)| 775 Mb

Model Quality Assurance (MQA) is an automated SPICE model validation software which allows you to check and analyze SPICE model library, compare different models, and generate quality assurance (QA) reports in a complete and efficient way. With more than ten years of history, MQA has become the industry standard for SPICE model acceptance and signoff and is widely adopted by leading integrated device manufacturers (IDMs), foundries and design houses.

Key Benefits of MQA
– Fully automatic model quality assurance and reporting process to improve the productivity
– Easily to identify the model issues with the customizable knowledge-based checking routines
– Ensure your EDA environment compliance across various foundries, technologies, process nodes and simulators

Language: English
Operating Systems: Windows 7/8.x 64Bit

 

Synopsys Synplify FPGA 2018.09 SP1 Win/Linux

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Synplify FPGA包含可选Synplify Pro和Synplify Premier FPGA综合工具。
Synopsys Synplify FPGA设计软件提供了一个高品质,高性能和易于使用的FPGA实现和调试环境。采用Synopsys的FPGA工具套件增益设计师快速进入超结果为复杂的FPGA,面积优化成本和降低功耗,自动化软错误缓解,分层设计能力和多FPGA厂商的支持。该的Synplify Pro和Synplify Premier FPGA设计工具,通过提供链接到高性能功能验证与VCS仿真和集成Synphony模型编译器的信号处理硬件的高层次综合提供额外的价值。
许多设计和验证团队越来越倾向于使用基于 FPGA 的原型验证,以便使产品及时进入市场。 基于 FPGA 的 Synopsys 原型验证解决方案可以使开发者尽早进行芯片制造前的嵌入式软件开发和软硬件协同设计,从而缩短上市时间并降低昂贵的器件改版费用。 同时,我们紧密集成且易于使用的HAPS硬件和软件工具套件可大幅加快从单个 IP 模块到处理器子系统再到整个SoC的软件开发、软硬件集成和系统验证。


Synopsys Synplify FPGA 2017.09/2018.09 SP1 Win/Linux (FPGA综合工具) | 1097 Mb
点击放大完整功能测试图片

Synplify Premier solution is the industry’s most productive FPGA implementation and debug environment. It includes all the features of Synplify Pro and additionally provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes.
The Synplify Premier software delivers fast turnaround time capabilities and feedback for users seeking to quickly implement the design on the board or to tune their design projects prior to final implementation. It addresses the most challenging aspects of FPGA design including timing closure and has the ability to perform graph-based physical synthesis for more accurate upfront timing prediction. It provides flows for fast logic verification and RT-Level debug. Under the hood, it contains optimization techniques that enhance DSP, IP and embedded design results. For ASIC prototypers, it delivers ASIC design file and DesignWare compatibility as well as tight integration with the Confirma Rapid Prototyping platform and FPGA vendor back-end tools as well as vendor embedded tools including Altera SoPC Builder and Xilinx EDK.
The Synplify Premier product offers FPGA Designers and ASIC Prototypers, targeting single FPGA-based prototypes, with the most efficient method of design implementation and debug. The Synplify Premier software provides in-system verification of FPGAs, dramatically accelerates the debug process, and provides a rapid and incremental method for finding elusive design problems.
The Synplify Premier software advantages include:
* technology and vendor independence
* in-system debug
* fast timing closure
* RTL analysis
* DSP-friendly synthesis algorithms
* superior Quality of Results (QoR)

Language: English
Operating Systems: Windows 7/8.x/10.x/RHEL 6.6+, 7.x/SLES 11.x and 12.x

Synopsys Identify 2018.09 SP1 Win/Linux

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Synopsys Identify是一个功能强大的FPGA验证工具,让您快速查找和纠正功能设计在硬件错误的系统运行速度。该识别软件提供了高级触发功能,因此您可以准确地专注于您要查看,你选择看它设计的时候部分。最重要的是,有解释结果不需要额外的努力。您添加探头仪器的设计和直接在RTL源代码中观察结果。

该Identify RTL调试器可以让你的仪器RTL HDL后,仍然在RT级,调试直播,运行硬件实现FPGA。在确定FPGA调试软件验证设计的硬件,类似于模拟 – 只有更快,具有在系统的刺激。

该Identify RTL调试器允许您指定样本触发器,导航设计图形,并标记在RTL是作为探测器的信号。合成后,结果查看和注解到RTL源代码,HDL的Analyst®RTL查看,或第三方,波形显示器。这样可以确保从RTL到实现等价和FPGA设计正确的操作。

主要特点:

– 支持Altera公司,Microsemi的和Xilinx器件
– 有能力的仪器,并直接从RTL源代码调试先进的FPGA设计
– 高级触发创作允许所需的设计运行情况下的观察和探测电路中的特定节点
– 能见度到内部设计,同时以全速运行
– 显示调试结果的叠加的RTL源,RTL结构图顶部,或具有波形观测器
– 有选择地在调试会话期间查看多达内部节点的8个不同的组,一个确定IICE
– 综合和布局旁路选项允许的Virtex-7/6/5 FPGA的快速仪表变化
– 兼容与Synopsys验证解决方案Verdi3™和Siloti为基于FPGA的原型自动调试和知名度


Synopsys Identify 2018.03/2018.09 SP1 Win/Linux (FPGA验证工具) | 210 Mb

Synopsys Identify RTL debugger allows you to instrument RTL HDL and then, still at the RT-Level, debug the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation – only much faster and with in-system stimuli.

The Identify RTL debugger allows you to designate sample triggers, navigate the design graphically, and mark signals in the RTL that are to serve as probes. After synthesis, the results are viewed and annotated onto the RTL source code, the HDL Analyst® RTL View, or third party, waveform viewer. This ensures RTL-to-implementation equivalence and correct operation of the FPGA design.

Key Features

  • Support for Altera, Microsemi and Xilinx devices
  • Ability to instrument and debug an advanced FPGA design directly from RTL source code
  • Advanced trigger creation allows the viewing of desired design operation scenarios and probe specific nodes in the circuit
  • Visibility into the internal design while operating at full speed
  • Display of debug results superimposed on top of RTL source, RTL structural view, or with a waveform viewer
  • Selectively view up to 8 distinct groups of internal nodes with a single Identify IICE during a debug session
  • Synthesis and placement bypass option allows rapid instrumentation changes of Virtex-7/6/5 FPGA
  • Compatible with Synopsys verification solutions Verdi3™ and Siloti for automated debug and visibility of FPGA-based prototypes

Download Identify Datasheet

Language: English
Operating Systems: Windows 7/8.x/RHEL 5.x-7.x

Altair Flux 2019.0 x64

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FLUX 2019是由Altair带来得一款专业的电,磁,热场分析软件,可用于各类电机,电器,传感器,舰船的分析,强大的后处理功能,提供可靠的技术支持服务,欧洲最流行的电,磁,热场分析软件。FLUX是一款针对于电机,传感器,变压器等电磁设备的专业二维及三维仿真软件它基于有限元算法,主要用于电磁设备,热装置,热处理的分析与设计主要应用领域有:。电磁,电热,电子机械和驱动设备等。基本模块包括前处理(建模,物理属性设置,网格剖分),求解以及后处理(结果显示,数据输出)。共有16大应用功能模块供用户选择。
作为Altair HyperWorks仿真平台的一部分,Flux是低频电磁和热仿真的领先软件,Flux 公司发布了Flux 2018.1.1。这个版本现在已经完全是HyperWorks的一部分,并且由于我们灵活的HyperWorks单元,用户现在可以访问更多的工具,这将帮助您节省设计时间并实现强大的模拟。
FLUX 允许用户使用Python命令流编写特殊的材料属性,定义驱动电源属性和定义边界条件,用于控制开发和执行特定的后处理任务。
FLUX_to_Simulink接口:用户可以通过Simulink的接口将FLUX模型作为独立模块应用到其他专业仿真软件中进行更高级的分析,如:优化设计,电机起动的瞬时控制等。这些功能使FLUX®成为目前国际市场上最具灵活性的软件。


Altair Flux 2019.0.0 x64 (电磁热场分析)| 1.35 Gb

The leading software for low frequency electromagnetic and thermal simulation, Flux, now a part of the Altair HyperWorks simulation platform, has released Flux 2019.0.0. This release is now fully part of HyperWorks and thanks to our flexible HyperWorks Units,users are now able to access even more tools that will help you to save time in your designs and enable powerful simulations.
Flux 2019 New Features:
– Accelerate your design when dealing with 3D complex CAD geometries
A number of new tools were introduced in Flux 12.3, which enabled the import of 3D meshes directly from HyperMesh and SimLab,bringing new capabilities for CAD geometry simplification and meshing. Flux 2018 improves the existing workflow, bringing moreflexibility as well as making it applicable to any type of application.
The following functionality is available: change the order of the mesh elements, build an infinite box after import, account for movement, deal with any type of coil description or importing a surface mesh.
– Solving faster in 3D using new HPC capabilities
Improvements introduced in Flux 2019 focus on large 3D models with eddy currents.
. New mathematical formulations are now available to help the non-linear convergence in such cases, particularly in the frequency domain.
. The linear solver has also been updated with the latest version of MUMPS, and the possibility to use it in a distributed memory mode, allowing Flux to run on clusters with larger numbers of cores. This brings great accelerations for 3D models with large meshes.
. It is now also easier to benefit from the computing power of remote clusters thanks to the connection of Flux with PBS Works,Altair’s industry-leading workload manager and job scheduler for high-performance computing.
– Going further in the coupling with mechanical simulation
The coupling with OptiStruct for mechanical design has been updated with the new version. For vibration analysis of electric machines, the post-processing capabilities of Flux have been extended with more options in the data visualization and export.
For static stress analysis, it is also now possible to export force densities from a magnetostatic model or from a step of a transient magnetic computation to a structural simulation. Not only magnetic pressures but also volumic Laplace forces can be calculated and exported to OptiStruct to compute mechanical stresses.
– Efficient power busbar design using Flux PEEC
The PEEC (Partial Element Equivalent Circuit) method is now directly available in Flux. Because this solver does not need any meshing of the air surrounding the parts, it is much more efficient than the finite element method to deal with sets of long or flat conductors. It is the tool of choice for the design of power busbars. Resistances, inductances and parasitic capacitances of conductors can be quickly computed and extracted for circuit simulation. Current, power or force densities distributions are natural outputs that can be used with thermal or structural solvers to analyze respective temperature distributions or mechanical stresses in the bars.
Note: For the full list of new and improved features, please refer to the release notes located in the folder of your Altair Flux 2019 or here here

Language: English/简体中文/Multilingual
Operating Systems: Windows 7/8.x 64Bit


Download Link (下载地址)
Altair_Flux_2018.0.0.2336_x64.part1
Altair_Flux_2018.0.0.2336_x64.part2
Altair_Flux_2018.1.1_x64_HotFix_Only

Catena SIMetrix-SIMPLIS Elite With DVM and Verilog 8.2

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Catena SIMetrix/SIMPLIS是一款用于优化设计电力电子电路的高级仿真工具。SIMetrix /SIMPLIS 完美结合了精度与收敛性能,实现了电源电路的高速仿真。 SIMetrix为专业的电子工程师提供混合模式电路仿真程序包。SIMetrix包含了一个增强型SPICE仿真器,原理图编辑器和波形显示器。拥有已为业界公认的优越性能和出色技术支持,SIMetrix是一种实惠高效的EDA解决方案。
SIMetrix是为广大电子工程师提供的一款增强型SPICE混合信号专业仿真设计平台,具有优秀的收敛性能和仿真速度。 SIMPLIS是专为开关电源系统设计开发的仿真引擎。作为电源系统设计与新产品开发的仿真标准,广泛应用于各类电源设计,通讯设备等领域。SIMetrix/SIMPLIS同时集成了灵活的原理图编辑功能和强大的仿真结果后处理工具。
◆SIMetrix/SIMPLIS软件特点
– SIMPLIS:快速电力电子电路仿真引擎
– SIMetrix:增强型SPICE与混合模式仿真器
多层电路原理图结构模式
-强大的波形处理功能,可在仿真前、仿真时及仿真后进行波形观测。
-先进的测量与数据处理功能
-开放式结构,利用脚本语言实现用户定制功能,如自动化及专用波形分析。


Catena SIMetrix-SIMPLIS Elite With DVM and Verilog 8.2 (电源仿真) | 290MB

Catena SIMetrix/SIMPLIS enables engineers to design and simulate switching power electronics systems. It combines accuracy and speed in a full-featured design environment, enabling 10-50x faster simulation than SPICE for power supply designs.
Key features
-All features of SIMetrix Classic and uses the same GUI environment including its hierarchical schematic editor and waveform viewer
-Transient analysis 10-50x faster than SPICE
-Periodic operating point (POP) analysis. Rapidly locates the steady state operating point of a switching system without having to simulate the startup transient conditions
-Small signal AC analysis. Unlike SPICE, operates on the full switching model and provides the same result as if making the measurement with transient analysis using a swept frequency generator. In other words, runs a frequency sweep just how you would do this on the bench. No need for error-prone averaged models
-The Advanced Digital Simulation Library provides a wide variety of digital functions such as counters, ADCs, DACs and much more.
-SPICE transistor and diode model conversion to SIMPLIS format. Converts SPICE models by running a SPICE simulation to perform parameter extraction.
Addons
-DVM can be added to this product.

Language: English
Operating Systems: Windows 7/8.x/10.x


CST IdEM 12.0 Win/Linux x64

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Idem是用于生成线性集总多端口结构的宏模型(例如,通过场,连接器,封装,不连续等)的用户友好工具,从其输入 – 输出端口响应中已知。 结构的原始特征可以来自测量或模拟,无论是在频域还是在时域中。 一套先进且条件良好的合理拟合模块可以适用于几乎任何类型的表征。 生成的模型采用通用SPICE格式,用于设计流程中所需的系统级仿真。 因此,Idem可以对任何类型的线性结构,组件,互连,封装进行SPICE处理,无论您的原生特性和应用领域如何。


CST IdEM 12.0 Win/Linux x64 (电气互连结构宏模型)| 1.45 Gb


Idem is a user friendly tool for the generation of macromodels of linear lumped multi-port structures (e.g., via fields, connectors, packages, discontinuities, etc.), known from their input-output port responses. The raw characterization of the structure can come from measurement or simulation, either in frequency domain or in time domain. A suite of advanced and well conditioned rational fitting modules grants applicability to virtually any kind of characterization. The resulting models are cast in common SPICE formats for the system-level simulations required in your design flow. Thus, Idem enables SPICE processing for any kind of linear structure, component, interconnect, package, whatever your native characterization and application area.

HomePage: http://www.cst.com
Language: English
Operating Systems: Windows 7/8.x/RHEL 6.x-7.x 64Bit

Mentor HDL Designer Series 2018.1

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Mentor HDL Designer Series 2018产品为个人或设计团队提供了一个集成且完全灵活的设计捕获和数据管理环境。与通用版本管理工具集成可确保设计流程所有阶段的可追溯性。

VHDL和Verilog显然都是基于文本的语言,所有人可以只需使用您喜欢的文本编辑器输入它。当然,这在某种程度上可以正常工作,但随着设计变得更大并且设计团队的设计工作,这变得越来越困难。

是时候改变你对HDL设计的看法了。借助HDL Designer Series,图形输入终于成熟,为用户提供了复杂的工具,可以降低生成高质量可合成HDL代码的复杂性,同时管理实施过程中产生的大量数据,但最简单设计。

HDL Designer Series介绍
HDL Designer Series包含一系列产品,支持HDL设计创建,管理和分析,这些产品是从Mentor Graphics的Renoir工具发展而来的。具有完整的版本控制功能,可与您的下游工具集成,用于仿真,综合和放置。路线,HDL Designer系列是整个HDL设计环境的驾驶舱。

HDL Designer Series包括:


     

  • HDL Author用于设计创作
    使用HDL文本,C代码,框图,状态图,算法状态机,流程图,真值表,IBD和任何组合,HDL Author允许您捕获设计和管理数据。它还包括图形编辑器中的模拟动画,以通过ModelSim,Precision Synthesis和Leonardo Spectrum最大限度地提高集成流程的优势。
  •  

  • HDL Detective用于设计分析,可视化和文档编制
    允许您导航和分析现有文本或图形设计,使用高级代码到图形创建基于文本的设计的图形数据库,以便将遗留代码导入其他HDL Designer工具。
  •  

  • HDL Designer,它将以上两者结合在一个包中
    包括从设计源创建文档的功能,包括用于自定义发布的详细程度的过滤器。包含DesignChecker后,标准化又向前迈进了一步。这是一个HDL规则检查器(有时称为Linting工具),它允许轻松验证手动编写的代码,以确保其与项目或公司编码标准的一致性。


Mentor HDL Designer Series 2018.1 (HDL设计环境)| 483 Mb

The HDL Designer Series of products provides an integrated and fully flexible design capture and data management environment for either individual or teams of designers. Integration with common version management tools ensures traceability of all stages of the design flow.
VHDL and Verilog are clearly both text based languages and you could – and people still do – just type it in using your favourite text editor. This of course works fine up to a point, however as the designs get bigger and designs are worked upon by teams of designers, this becomes increasingly more difficult.
It’s time to change the way you look at HDL design. With HDL Designer Series, graphical entry finally comes of age, providing the user with sophisticated tools that take the complexity out of generating high-quality synthesizable HDL code, combined with managing the vast amount of data produced during the implementation of all but the most simple designs.

Introducing HDL Designer Series
HDL Designer Series comprises a series of products enabling HDL design creation, management and analysis, which has evolved from the Renoir tools from Mentor Graphics. With full revision control capabilities, integration with your downstream tools for simulation, synthesis and place & route, HDL Designer Series is the cockpit for the whole HDL design environment.

The HDL Designer Series comprises:

  • HDL Author for design creation
    Using HDL text, C code, block diagrams, state diagrams, algorithmic state machines, flowcharts, truth tables, IBD and any mix, HDL Author allows you to capture the design and manage the data. It also includes simulation animation within the graphical editors to maximise the benefit of the integrated flow with ModelSim, Precision Synthesis and Leonardo Spectrum.
  • HDL Detective for design analysis, visualization and documentation
    Allows you to navigate and analyse existing text or graphical designs, using advanced code to graphics to create a graphical data base of text based designs for importing legacy code into other HDL Designer tools.
  • HDL Designer which combines both of these in a single package
    Includes the capability of creating documentation from design sources, including filters to customise the level of detail published. Standardisation is taken a step further with the inclusion of DesignChecker. This is an HDL Rule Checker (sometimes known as a Linting Tool) which allows manually written code to be easily verified for its consistency with the project or company coding standards.

HomePage: http://www.mentor.com
Language: English
Operating Systems: Windows 7/8.x 64Bit/RHEL 5.x-7.x

Mentor Graphics Precision Synthesis 2018.1

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Mentor Graphics Precision Synthesis– 新一代FPGA综合技术
Precision Synthesis Linux是Mentor Graphics最新推出的新一代FPGA综合技术,提供包括RTL综合、物理综合以及高级语言综合在内的一整套综合解决方案。Precision Synthesis具有直观的用户界面,高质量的综合结果以及准确的时序分析,并且能解决目前最新的大规模、高性能FPGA的时序收敛问题, 节省了以前在综合和布局布线间多次迭代反复所花费的时间。由于在开发期间就充分考虑了使用者的需求,Precision Synthesis从安装到完成设计综合,整个过程都非常流畅。设计人员可以专注于自己的设计,不必在学习工具的使用上花费时间。Precision Synthesis集强大的综合功能和易用性于一体,可以帮助用户在最短的时间内完成最具挑战性的FPGA设计。

Precision Synthesis 包括下面的系列产品:
Precision RTL 是集强大的综合技术以及准确的时序分析于一身的RTL综合工具。
Precision Physical 物理综合工具。引入布局布线后的信息和延时信息,重新进行综合。在更精确的时序基础上,采用先进的算法,必要情况下在综合工具内改变布局布线,功能强大的自动流程和交户式操作相结合,解决目前最新的大规模、高性能FPGA的时序收敛难题, 节省了以前在综合和布局布线间多次迭代所花费的时间。
除了具有Leonardo Spectrum在FPGA综合方面的所有功能,如模块综合、团队设计、混合语言综合等,Precision Synthesis还包含许多新的技术和特点。

主要特点:
• 直观的用户界面。Precision Synthesis的图形化界面(GUI)简洁直观,用户可以在一个界面下完成所有的操作。
• 内容敏感的工具条窗口。Precision Synthesis图形化界面中有一个内容敏感的工具条窗口,窗口里的内容会在设计的各个阶段动态更新,从而引导使用者完成整个设计过程。
• 新的逻辑综合技术。Precision引进许多新的逻辑综合技术,如:跨层次综合、强大的状
态机优化技术、Tunneling、Re-timing、Replication、Re-structuring、LUT merging等,其中很多技术以前只用于ASIC综合。
• 高质量的综合结果。Precision 全新的优化引擎具有A.S.E.(Automatic Signature Extraction)的功能,能够自动识别各种电路结构以及器件的内部资源,对不同的电路采用不同的优化技术,最终满足设计的性能要求。以前很多需要人工干预的工作,现在都可以自动完成。
• 内嵌业界最先进的RTL原理图和工艺级原理图浏览器。用户可以根据需要用多种方式察看原理图,迅速得到自己关心的内容。
• 方便灵活的加约束的方式。用户可以通过设计层次浏览器、原理图、图形化的窗口、命令行以及约束文件等多种方式设置约束体条件。不论何种方式施加的约束都可以被保存形成约束文件。
• 准确的时序分析。Precision新的时序引擎能够对最复杂的时序结构做出准确的时序分析:支持相对于时钟沿的约束;支持多个同步时钟或异步时钟的电路分析。
• 支持Xilinx 的DCM。在DCM输入端所加的约束可以传递到输出端。
• 支持SDC约束。Precision支持SDC这一业界标准的约束文件格式。
• 支持增量分析。如果仅对部分电路的约束条件作了修改,不必重新进行综合,仅对发生变化的部分重新分析。
• 生成多种时序报告:不满足时序的报告,未加的约束报告,
• 时序报告可以追踪到原理图或者物理布局布线图中。
对FPGA厂家的设计工具的高度集成。只要用鼠标轻轻一点,就可以使用厂家的时序分析和布局规划等工具。


Mentor Graphics Precision Synthesis 2018.1 x64/2017.1 Linux64 | 433 mb

Mentor Graphics Precision Synthesis offers high quality of results, industry-unique features, and integration across Mentor Graphics’ FPGA Flow– the industry’s most comprehensive FPGA vendor independent solution.
Precision RTL Synthesis is a synthesis platform that maximizes the performance of both, existing programmable logic devices (CPLDs and FPGAs) and next-generation, multi-million gate field programmable system-on-chip (FPSoC) devices. Precision RTL Synthesis is a comprehensive tool suite, providing design capture in the form of VHDL and Verilog entry, advanced register-transfer-level logic synthesis, constraint-based optimization, state-of-the-art design analysis, schematic viewing and encapsulated place and route.

Mentor Graphics Precision Synthesis 2018.1 x64 安装说明:

1.解压缩Precision-win64-2018.1.rar,点击Precision-win64-2018.1.exe安装。

2.拷贝patched.rar的文件到安装目录\MentorGraphics\PS2018.1_64-bit\Mgc_home\,解压缩后覆盖相同文件。

3.运行c:/flexlm/MT_KG.exe得到license.txt,设置环境变量。

4.运行软件。

HomePage:https://www.mentor.com/
Language: English
Operating Systems: Windows 7/8.x 64Bit/RHEL 5.x-7.x

CST STUDIO SUITE 2019 SP2 Win/Linux

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计算机仿真技术公司(CST)欣然宣布其旗舰电磁仿真软件CST STUDIO SUITE 2019正式发布。 CST STUDIO SUITE 多年的研究和发展,包括在各个层面的改进和创新,从优化求解技术新的功能区为基础的GUI。 这些进步提升CST STUDIO套件的性能,易用性和多功能性,毫不妥协,并引导您轻松通过复杂的电磁系统。
CST STUDIO SUITE被广泛应用在通信和电子医疗保健和航空等领域工作的工程师,帮助他们电磁现象的建模和评估他们的设计,以获得最佳性能。 结合高频和低频模拟工具以及专门求解器的应用,如印刷电路板,电缆和带电粒子设备,可以应用到许多典型的工程任务,如EMC / EMI评估,SI和PI的分析,设计CST Studio套件优化,天线及滤波器的调谐。

CST Studio Suite2019是一款功能强大的电磁仿真软件,在软件上你可以找到很多设计工具帮助你执行电磁设计以及后数据处理,无论是设计图纸还是建立模型都是很方便的,该软件提供丰富的模型设计工具,你可以选择3D设计,可以选择求解器,可以选择电路分析,所有软件都可以在启动新项目的时候找到,让用户在进行电磁分析的时候可以轻松从多款软件找到适合自己使用的设计工具,并且软件也提供大量的设计案例,你可以点击软件的帮助查看相关项目工作流程,从而知道如何在CST Studio Suite2019建立新的项目!

软件功能
  CST Filter Designer 3D是带通和双工器滤波器设计的综合工具,支持交叉耦合和高级拓扑。

  交互式直观界面可帮助您快速实现规范的设计目标。

  CST芯片接口是一种软件工具,可以从2D芯片布局开始加速复杂3D芯片模型的生成。它通过帮助工程师基于物理建模设计芯片来提高效率,

  FEST3D是一种基于波导和同轴腔设计复杂无源微波元件的软件工具

  技术(如多路复用器,耦合器,滤波器),计算时间非常短,精度高。

  它提供了无源组件设计所需的所有功能,例如组件的自动合成,优化和公差分析模块。

  SPARK3D是一种独特的仿真工具,能够确定各种无源RF器件的击穿功率水平。通过从CST STUDIO SUITE,FEST3D或其他求解器输入电磁场,SPARK3D能够分析真空击穿(多重反应器)和气体放电。

  System Simulator是研究复杂系统动态行为的正确工具。

  系统模拟器可以结合电,热,磁和逻辑组件,使其非常适合机电组件的设计。

  IdEM是一种用户友好型工具,用于生成电气互连结构的SPICE就绪宏模型,例如封装,连接器,通路场,不连续性,背板链路和完整的电力传输网络。

  IdEM从输入输出端口响应开始,从测量或模拟得出,提供准确,可靠,被动和因果宽带计算模型,可用于任何电路仿真环境,实现可靠的瞬态和AC分析。


CST STUDIO SUITE 2019 SP2 Win/Linux (电磁仿真)| 3.3 Gb

Computer Simulation Technology (CST), part of SIMULIA, a Dassault Systèmes brand, announces the release of its flagship EM simulation software, CST Studio Suite 2019.

CST Studio Suite 2019 – What’s new:

CST Studio Suite 2019 builds on industry-leading simulation technology with a range of new features for the design, simulation and optimization of components and systems. New features include encrypted data sharing, the next generation of Perfect Boundary Approximation (PBA), full integration of the voxel body model poser, and the hybrid solver for bidirectional hybrid coupling between all the general purpose high-frequency solvers. The 2019 release is also available on the Dassault Systèmes 3DEXPERIENCE platform, allowing direct links to other design and simulation tools.

These tools increase the agility of CST Studio Suite for modeling and simulating complex systems, and allow electromagnetic simulation to be applied in large projects spanning multiple departments and suppliers.

About CST Studio Suite. The electromagnetic (EM) simulation software CST STUDIO SUITE is used by industry-leaders to design, analyze and optimize components and systems across the EM spectrum. The CST Complete Technology approach means that all solvers are available within a single graphical user interface, with strong links between different solvers. The 2018 release of CST STUDIO SUITE develops on previous success with a range of new features for simulating entire systems with hybrid methods.

One key strength of CST STUDIO SUITE is the ability to link multiple simulations with different solvers into a single workflow with System Assembly and Modeling (SAM). In 2018, the improved Assembly Modeler offers users a more efficient way to combine multiple components into a system employing a 3D environment optimized for complex models. This is complemented by new features for EM/circuit co-simulation and the Hybrid Solver Task providing bidirectional solver coupling between the Time Domain and Integral Equation Solvers – a major step forward for hybrid simulation.

For bio-EM simulations, the voxel poser tool, previously a separate product, is now integrated directly into the CST STUDIO SUITE interface, offering users direct access to the voxel poser during the modeling process. Body models using the tetrahedral mesh can now move realistically to simulate breathing, which is important in the design of medical devices.

Filter Designer 3D, CST’s tool for designing cross-coupled filters and calculating coupling matrices, is now connected directly to the powerful optimizers in CST STUDIO SUITE. This means that the optimizers have access to the coupling matrix calculation, allowing faster and more intelligent filter tuning.

Photonic and terahertz applications are a growing trend, and CST STUDIO SUITE offers a new alternative interface for these areas, with direct access to optical features. It also now allows simulations to be set up using wavelength rather than frequency. CST STUDIO SUITE 2018 introduces the ability to calculate farfields on multilayer substrates, which is useful both for photonic applications and for simulating antennas printed on complex PCBs.

Behind the scenes, the core of the software is as ever fine-tuned to optimize performance on the latest hardware, and CST STUDIO SUITE is being introduced to the Dassault Systèmes 3DEXPERIENCE platform with links to other SIMULIA tools.

HomePage:https://www.cst.com/
Language: English
Operating Systems: Windows 7/8.x 64Bit/RHEL 5.x-7.x

Xilinx Vivado Design Suite HLx Editions 2018.3

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Xilinx Vivado Design Suite 2018.3是赛灵思公司生产的一款软件套件,用于综合和分析HDL设计,取代赛灵思ISE,并具有片上系统开发和高级综合的附加特性。Vivado代表了对整个设计流程(与ISE相比)的彻底改写和重新思考,并且被评论家描述为“精心构思,紧密集成,快速,可扩展,可维护和直观”。这是赛灵思推出Vivado设计套件2018.3 HLx版本。此发行版包含许多改进功能,可提高UltraScale +设备的结果质量并缩短运行时间。Vivado 2018.3还具有其他易用性改进功能,以确保您可以提高整体效率并更快地将产品推向市场。新的HLx版本为设计团队提供了利用基于C的设计和优化重用,IP子系统重用,集成自动化和加速设计关闭所需的工具和方法。结合UltraFast高级生产力设计方法指南,这种独特的组合可以使设计人员在高度抽象的同时促进设计重用,从而提高生产力。

功能介绍
Vivado设计套件是赛灵思公司生产的一款软件套件,用于综合和分析HDL设计,取代赛灵思ISE,并具有片上系统开发和高级综合的附加特性。与依靠ModelSim进行仿真的ISE不同,Vivado系统版本包含一个内置的逻辑仿真器。Vivado还引入了高级综合,并带有一个将C代码转换为可编程逻辑的工具链。Vivado被描述为“最先进的全面EDA工具,在数据模型,集成,算法和性能方面拥有所有最新的花样和哨子”。Vivado设计套件HLx版本包含部分重配置,Vivado HL设计版和HL系统版无需额外费用。保修期内的用户可以重新生成许可证以访问此功能。部分重新配置适用于Vivado WebPACK版本,价格低廉。

Vivado Design Suite通过全新 HLx 版本为基于 IP 的新一代 C/C++ 设计实现了一种新型的超高生产力方法,其中包括:HL System 版本、HL Design 版本以及 HL WebPACK 版本。

Vivado HLx 版本可为设计团队提供实现基于 C 的设计、重用优化、IP 子系统重复、集成自动化以及设计收敛加速所需的工具和方法。与 UltraFast™ 高层次生产力设计方法指南相结合,这种特殊组合经过验证,不仅可帮助设计人员以高层次抽象形式开展工作,同时还可促进重复使用,从而可加速生产力。
加速高层次设计
软件定义 IP 生成 – Vivado 高层次综合 (HLS)
基于模块的 IP 和 Vivado IP 集成
基于模型的 DSP 设计和 System Generator for DSP集成
加速验证
Vivado 逻辑仿真器
集成混合语言仿真器
集成 & 独立 编程与调试环境
加速验证超过 100 倍,通过 C、 C++ 或 SystemC 以及 Vivado HLS
加速实现
设计实现时间缩短 4 倍
设计密度提升 20%
在低端 & 中档产品中实现高达 3 速度级性能优势,在高端产品中实现 35% 功耗优势


Xilinx Vivado Design Suite HLx Editions 2018.3 (综合和分析HDL设计)| 18.3 Gb

Xilinx, Inc. has released update for Vivado Design Suite HLx Editions 2018.3, enabling a new ultra high productivity approach for designing All Programmable SoCs, FPGAs, and the creation of reusable platforms.
These new HLx Editions include HL System Edition, HL Design Edition and HL WebPACK Edition. All HLx Editions include Vivado High-Level Synthesis (HLS) including C/C++ libraries, Vivado IP Integrator (IPI), LogicCORE IP subsystems, and the full Vivado implementation tool suite to enable mainstream users to readily adopt the most productive and advanced C and IP-based design flows. When coupled with the new UltraFast High-Level Productivity Design Methodology Guide, users can realize a 10-15X productivity gain over traditional approaches. The HLx Edition is available as a no-cost upgrade to the Vivado Design Suite.
Ultra High Productivity for Creating and Programming Reusable Platforms
Over the last 4 years, leading edge Xilinx customers have pioneered and matured the enabling C and IP-based design technologies and methodologies now included in the HLx Editions, and proven the 10-15X productivity potential. To realize this productivity, these customers adopted all or a subset of the following;
– C-based design and optimized reuse,
– reuse of IP subsystems,
– integration automation, and accelerated design closure.

Unlike tradition RTL-based design where the majority of the design effort is spent in the backend of the design process, C and IP-based design enables vastly superior design reuse to speed creation, rapid design exploration for better micro-architectures, replaces error prone manual C to RTL conversion, eliminates time and errors while integrating C and RTL-based IP, and dramatically shortens verification time. Using high levels of abstraction, customers have found that they can quickly get overall better or equal Quality of Results (performance, power, utilization).

To enable these high productivity flows, the HLx Editions include Vivado HLS, Vivado IPI, LogicCORE IP subsystems, and the full Vivado implementation tool suite. In addition, Xilinx and its Alliance ecosystem are continuously expanding market-specific C libraries such as OpenCV for video and image processing and Machine Learning for Automotive Driver Assistance Systems (ADAS) and Data Center applications. Xilinx’s new LogiCORE IP subsystems are highly configurable, market-tailored building blocks that integrate up to 80 individual IP cores, software drivers, design examples, and test benches. New IP subsystems are available for Ethernet, PCIe, video processing, image sensor processing, and OTN development. These IP subsystems are based on industry standards such as AMBA AXI 4 interconnect protocol, IEEE P1735 encryption and IP-XACT to enable interoperability with Xilinx and Alliance member IP and to accelerate integration.

The combination of C-based IP and pre-packaged IP subsystems are rapidly combined leveraging Vivado IP Integrator for integration automation. Vivado IPI’s integration automation provides a device and platform aware, interactive environment that supports intelligent auto-connection of key IP interfaces, one-click IP subsystem generation, real-time DRCs, and interface change propagation, combined with a powerful debug capability. The platform aware intelligence, can preconfigure the Zynq SoCs and MPSoCs processing system with the correct peripherals, drivers, and memory map to support the target board. Design teams can now rapidly identify, reuse, and integrate both software and hardware IP, targeting the ARM processing systems and high-performance FPGA logic.

HLx Complements SDx for Creating and Deploying Platforms

HLx speeds the creation, modification, and programming of All Programmable platforms for hardware engineers, complementing the Xilinx SDx Development Environments (SDSoC, SDAccel and SDNet) which are tailored for software and systems engineers. The SDx family of development environments enable software-defined programming of HLx generated platforms using a mix of C, C++, OpenCL, and the emerging P4 language for packet processing. HLx and SDx represent Xilinx’s new era of design enablement solutions for developing smarter, connected and differentiated systems leveraging a new era of All Programmable devices including Zynq SoCs, MPSoCs, ASIC-class FPGAs and 3D ICs.

HomePage:https://www.xilinx.com/
Language: English
Operating Systems: Windows 7/8.x 64Bit