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Concept RTLvision 6.9.2 Win/Linux

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Concept RTLvision PRO提供RTL的快速可视化,以便工程师可以轻松地了解和实现现有的代码元素,无论是在VHDL,Verilog还是系统Verilog。它不再可能从头开始执行所有ASIC和SoC设计:元素 先前的设计必须被重复使用,并且第三方IP块被非常频繁地嵌入。 但是了解第三方IP或遗留代码的RTL并不总是容易的,使得它耗费时间并且难以修改和集成到新的设计中。


Concept RTLvision 6.8.12/6.9.2 Win/Linux | 44.8 mb

Concept RTLvision PRO provides fast visualization of RTL, so that an engineer can easily understand, and implement existing code elements, whether in VHDL, Verilog or System Verilog.It is no longer possible to carry out all ASIC and SoC designs from scratch: elements of previous designs have to be re-used and third party IP blocks are embedded very often. But understanding the RTL for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design.

Language: English
Operating Systems: Windows 7/8.x/10.x 64bit

Concept StarVision 6.9.2 Win/Linux

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Concept StarVision PRO使工程师能够快速,轻松地了解和调试混合模式设计,并将IP构建块集成到其复杂的SoC和IC中。


Concept StarVision 6.8.12/6.9.2 Win/Linux | 47.8 mb

Concept StarVision PRO provides engineers with the ability to quickly and easily understand and debug mixed-mode designs and to integrate IP building blocks into their complex SoCs and ICs.
RTL, Gate-Level and SPICE-Level in one Integrated Debugging and Visualization Tool — Due to the increasing use of building blocks in SoC design, engineers need to work at different design levels (RTL, gate, transistor, analog, parasitic) as well as with different design languages and netlist formats. To support this challenge, Concept Engineering developed StarVision PRO, an integrated debugging cockpit for mixed-signal and digital design that makes analysis and debugging of complex SoC and IC designs easy and more transparent.
Easy Design Exploration — The interactive design navigation window shows schematic fragments of just the critical portion of the design while, at the same time, providing links to the original source code fragments (RTL, Netlist, SPICE) and to simulation results.

Language: English
Operating Systems: Windows 7/8.x/10.x/Linux

Dorado Twaker 1108.2016c Linux

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Tweaker Tweaker作为业界主流的ECO自动优化工具,其采用了独特的ECO 技术架构,并基于设计的静态时序分析和布局布线等sign-off数据,对设计进行ECO domain的划分,对设计进行局部的、增量的且安全的MMMC优化。Tweaker在优化的过程中充分考虑Physical Aware及Power Aware特性, 显著地降低迭代时间和减少额外错误被引入的机会。
主要功能优势:
– 采用MMMC技术在一次运行中实现多种ECO优化
– Minimum ECO logic专利技术算法
– 单一License可覆盖超过200种应用场景(scenarios)
– 基于Physical Aware与Power Domain Aware(CPF/UPF)的优化策略
– 基于signoff数据采用局部、增量和安全的优化分析
– 支持主流的静态时序分析工具与布局布线工具
– 支持跨越设计边界的ECO优化
– 超过500次成功tape-out验证,工艺涵盖110nm到7nm
– 友好的GUI提供高效的分析及手动ECO能力


Dorado Twaker 1108.2016c Linux (ECO自动优化工具)| 45 Mb

Dorado Tweaker is fundamentally architected for ECO incremental jobs. It relies on the signoff quality input data to perform “local optimization” which focuses only on the critical parts of the design. The approach minimizes the turnaround time, correlation issues, and the impact to the performance, while maximizing the tool capacity.
It nclude:
Timing ECO – Tweaker-T1
Power ECO – Tweaker-P1 Leakage Power Optimization
Functional ECO – Tweaker-F1
Metal ECO – Tweaker-M1

Language: English
Operating Systems: RHEL 5.x-7.x

Motor-CAD/Motorcad 11.2.6

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Motor-CAD 在计算稳态的热的结果时几乎可以提供立即的仿真速度。结果以图表显示,让你很容易的估算电机部件或不同区域的热的特征。
Motor-CAD 有提供瞬时解的能力。简单的瞬态、工作循环和全面的仿真都可以进行。
你可以选择转矩衰减或转速衰减分析。只需要定义希望分析的瞬态的性质,Motor-CAD就可以全面计算已定义电机各部件的热的瞬态情况,并且能提供解的过程中每一步的温度解。
Motor-CAD使用最新的接口技术,能快速、容易的登陆输入编辑界面。用户会很方便的输入和审核关键装置的参数及信息。
电机的3D图形通过单独的径向和轴向的剖面图构建。预览模式允许你监视参数变化的影响。
Motor-CAD可进行精确的3D热仿真
Motor-CAD的热技术建立在集总电路参数理论上。传导、强迫和自然对流及辐射都应用了高效、精确的数值算法。
程序使用了一系列已证实的热转换公式。物理装置的流体动力学仿真和测试数据均证实了Motor-CAD仿真结果的精确。
Motor-CAD现在支持无刷永磁电机、感应电机和开关磁阻电机。直觉的界面允许你在已有的模块里输入相关的电机数据。用户可以通过控制输入参数来描述自己设计的电机的特性,如:
-3D几何特征
-导体类型、绕组布置和功率控制
-机械的和电的损耗
-材料特性
-机座、端盖和冷却结构


Motor-CAD/Motorcad 10.5/11.1.5/11.2.6 含简体中文(电机电磁性能和冷却优化)| 159 Mb


Motor-CAD is a unique software package dedicated to the electromagnetic performance of motors and generators and the optimisation of their cooling. Developed more than 12 years ago, Motor-CAD is used by major motor manufacturers and universities worldwide.
Motor-CAD provides the ability to quickly and easily perform electromagnetic and thermal performance tests on prototype designs. Accurate electromagnetic and thermal calculations can be done in seconds. The results are presented in an easy to understand form for analysis to allow design decisions to be taken in an efficient manner.
The software has a carefully constructed user interface that makes for easy data input and interpretation of results. Many of the features that make Motor-CAD the perfect optimisation tool have been developed in close consultation with customers to meet the needs of the industry. This image shows the 3D view of the motor from within Motor-CAD.
Motor-CAD Ver.10.5 Update contents
– Improved phasor table display when 3 phases.
– Correction for liner and slot insulation weights, not taking into account number of slots.
– Added automatic Nx3 phase winding option.
– Added number of stator and rotor lamination sheets calculation.
– Fix for running calibration model from ActiveX DoSteadyStateAnalysis call.
– Correction in on load stator and rotor force calculations for multiple slices.
– Fixed TVent magnet and rotor surface area adjustment factors.
– Fix for Lab max current check with turns per coil scaling.
– Improved mag winding form, replaced combo boxes with radio groups.
– Improved calculation of BPM phase current when using square wave drive.
– Correction for Lab threading with different regional settings.
Language: English/简体中文/Multilingual
Operating Systems: Windows 7/8.x/10


Motor-CAD/Motorcad 11.1.5 – Download 百度云
链接: https://pan.baidu.com/s/1xanMuHpy_SXDAQQTI8PiZA 提取码: e3dy

ANSYS Electromagnetics Suite 19.0 Linux64

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Ansys电磁仿真套件Electromagnetics(原来的Ansoft)
ANSYS是电磁仿真软件行业的引领者,供应从电路级到系统级的仿真工具。工程师可依靠我们的系统仿真产品和电磁场求解器来设计通信和网络系统、集成电路(ICs)、印制板(PCBs)及机电系统。
ANSYS信号完整性设计软件是设计高速串行通道、并行总线及现代高速电子设备中完整电力分配系统的理想工具。
我们的射频、微波和天线设计软件可以帮助工程师设计、仿真和验证通信系统、移动设备、计算机、无线电和雷达中的高频组件和天线。
机电、电力电子和机电一体化工具是完成汽车、航空航天和工业自动化市场中组件和系统设计的行业标准。


ANSYS Electromagnetics Suite 18.1/19.0 Linux64 (电磁仿真套件) | 1.75G

ANSYS Electromagnetics providing new, unique capabilities and enhancements that offer the most advanced approach to guide and optimize product designs.
ANSYS is the leading provider of electromagnetic simulation software, engineers rely on our electromagnetic field solvers and system simulation products to design communication and networking systems, integrated circuits (ICs), printed circuit boards (PCBs) and electromechanical systems.
ANSYS signal integrity analysis products are ideal for designing high-speed serial channels, parallel buses and complete power delivery systems found in modern high-speed electronic devices.
Our RF and Microwave design and simulation software enables engineers to design, simulate and validate high-frequency components and antennas found in communication systems, mobile devices, computers, radio and radar.
ANSYS electromechanical simulation software is ideal for the design of electromechanical and power electronics components and systems common to the automotive, aerospace and industrial automation industries.

Language: English
Operating Systems:RedHat Entrprise Linux 5.x-7.x 64Bit


Integrand EMX With Virtuoso Interface 5.3 Linux64

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Integrand EMX是高频,射频和混合信号集成电路的电磁仿真器。它独特的重点是加之无与伦比的速度和精度完全自动化。 EMX得到了广大客户的基准比一个数量级比业界领先的有限元和边界元工具,更快更多。 EMX是建立在最大的自动化的理念,与业界标准的输入和输出格式,在命令行脚本化饱满,与现代IC布局功能自动处理。需要预先安装Cadence Virtuoso IC 6.1.x Linux。


Integrand EMX With Virtuoso Interface 5.2/5.3 Linux64 (电磁仿真器) | 34.0MB

Integrand EMX is an electromagnetic simulator for high-frequency, RF, and mixed-signal integrated circuits. Our unique emphasis is on complete automation coupled with uncompromised speed and accuracy. EMX has been benchmarked by our customers to be more than an order of magnitude faster than the leading finite-element and boundary element tools in the industry. EMX is built on a philosophy of maximal automation, with industry-standard input and output formats, full scriptability from the command line, and automated handling of modern IC layout features.

Language: English
Operating Systems: RedHat Entrprise Linux 5.x-7.x
System Requirements:Cadence Virtuoso IC 6.1.x Linux


Synopsys SiliconSmart 2017.12 SP2 Linux64

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SiliconSmart ADV是一种综合性标准单元库特性表征和品质保证(QA)解决方案,这种改进型解决方案可以生成PrimeTIme签核品质库,并在可用计算资源上提供最大的吞吐量。SiliconSmart ADV独特的授权许可方法可以轻松地适应不同的工作任务量,从而免去了特性表征团队的负担,使他们无须去预测未来的工作量要求以及在传统的繁琐授权许可方法限制下操作。此外,创新性SiliconSmart技术利用内嵌的黄金参考SPICE引擎,来为生成先进的LibertyTM模型提供特性表征加速,PrimeTIme静态时序分析(STA)使用该模型来准确地解释超低电压FinFET工艺对时序的影响。这包括PrimeTIme参数片上变异(POCV)、先进的波形传播(AWP)和电迁移(EM)分析。
SiliconSmart ADV通过一个同一许可证,提供了最先进标准单元库的库特性表征和品质保证所需的一切东西。为了实现最佳的准确性和最快的吞吐量,SiliconSmart ADV包括内嵌的Synopsys FineSim SPICE和Synopsys HSPICE电路仿真解决方案。它还提供灵活的多核许可来优化大型计算中心环境中的吞吐量,并轻松地适应不断变化的特性表征需求。SiliconSmart ADV综合性的LVF特性表征和建模性能实现了一流的PrimeTIme POCV变异分析。智能LVF性能优化技术提供最高的吞吐量和准确性。为了支持单元层EM特性表征,对最新的Liberty EM模型扩展的支持也被包括了进来。SiliconSmart ADV还提供一套工具加速签核品质库的手工执行及易于出错的品质保证过程。整个库认证过程将自动进行并行化处理,以提供快速的周转时间并尽早确定问题。可视化的辅助措施和智能化组织产生的结果有助于快速隔离问题区域,并提供品质保证管理度量指标。


Synopsys SiliconSmart 2017.12 SP2 Linux64 (ADV单元库特性表征解决方案)| 640 Mb

SiliconSmart is a comprehensive characterization solution for standard cells, I/O, complex cells and memory. It generates accurate model libraries tightly correlated with Synopsys’ digital implementation tools. Its built-in FineSim; simulation technology and tight integration with the gold-standard HSPICE; circuit simulator enable characterization and signoff accuracy. SiliconSmart supports all of the standard models, including NLDM (non-linear delay model), CCS (composite current source) and AOCV (advanced on-chip variation) models.
Benefits

  • SiliconSmart’s precise characterization and modeling capability combined with HSPICE golden accuracy is critical for producing signoff-quality library models, including timing, power, signal integrity and OCV to ensure best PrimeTime accuracy during static timing and power analysis. This unique platform-level integration of SiliconSmart produces the best correlation between PrimeTime and HSPICE for advanced technology nodes

Comprehensive solution

  • SiliconSmart is a comprehensive, unified solution that generates libraries for standard cells, I/Os and complex cells, such as multi-bit flip-flops and memories

High performance with pre-characterization optimization

  • SiliconSmart increases performance by using innovative pre-characterization optimization and intelligent optimization techniques that reduce the number of simulation runs required during the library characterization phase

Advanced node-ready

  • SiliconSmart is ready for characterizing and modeling libraries at advanced technology nodes, such as 16-nm and 14-nm. It supports generation of POCV coefficients and supports the latest FinFET models

Language: English
Operating Systems:RHEL 5.x-7.x 64Bit

Synopsys Custom WaveView/CustomExplorer 2017.12 SP2

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Custom WaveView 是一个针对模拟和混合信号 IC 的图形化波形观测仪和仿真后处理工具。Custom WaveView 的功能包括快速加载、显示滚动、大型波形文件的缩放、多种仿真器格式支持及一系列丰富的模拟和混合信号分析功能。
优势

  • 高性能的波形数据库 I/O,可快速访问大量仿真数据
  • 广泛的混合信号显示功能和分析功能,可从仿真结果中提取测量值
  • 可用于多个仿真器的单个波形工具
  • 嵌入式 HSPICE .MEASURE 指令支持和 .ALTER 仿真器的参数绘图
  • 瞬态、AC、RF、混合信息显示和分析
  • 用于编程复杂用户后处理脚本的可选 Tcl API
  • 灵活的波形分组 – 从同一个电路排线表或不同电路排线表上运行的不同仿真器中增加多个波形视图

Synopsys Custom WaveView/CustomExplorer 2017.12 SP2 Win/Linux64 (图形波形查看及后处理)| 120 Mb

Custom WaveView is a graphical waveform viewer and simulation post-processing tool for analog and mixed-signal ICs. Custom WaveView features fast loading, display scrolling, and zooming of very large waveform files, multiple simulator format support, and a rich set of analog and mixed-signal analysis features.
Benefits

  • High-performance waveform database I/O to quickly access large amounts of simulation data
  • Extensive mixed-signal display functions and analysis capabilities to extract measurements from simulation results
  • Single waveform tool for multiple simulators
  • Built-in support for HSPICE .MEASURE command and parametric plots for .ALTER simulations
  • Transient, AC, RF, mixed-signal display and analysis
  • Optional Tcl API for programming complex user post-processing scripts
  • Flexible waveform grouping—add multiple waveform views, either from different simulator runs on the same circuit netlist or from different netlists

Language: English
Operating Systems: Windows 7/8.x 64Bit/RHEL 5.x-7.x

Synopsys SpyGlass 2017.12 SP2 Linux64

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SpyGlass平台针对VERILOG和VHDL用先进的静态和动态分析来检查和诊断设计中可能存在的潜在问题,然后用其分析和追踪引擎来追踪问题的根源,最后给出一个解决问题的方法和建议。SpyGlass能够指出SOC问题中的非常复杂的问题,例如跨时钟域问题、同步问题以及SOC设计中的集成问题。并且,SpyGlass还可以检查电子设计规则(ERC)来确保设计符合工业设计标准或者用户自己定义的标准。

SpyGlass还提供了四个功能强大的选项:
(一)SpyGlass CDC提供了业界最完整的多时钟域解决方案,能自动识别各种同步手段(包括HandShake,FIFO),能采用Formal引擎验证同步方法在功能上的正确性。
(二)SpyGlass Constraints帮助设计人员在设计的整个流程中生成,验证和管理他们的约束文件。
(三)SpyGlass DFT提供了能够预测ATPG的测试覆盖率分析的能力,基于这个选项,用户可以很容易地预计所作设计的可测试性并且利用工具提供的指导来提高设计的可测试性。
(四)SpyGlass LowPower能够让用户能够快速分析出设计中的功耗效率问题,从而在还没有达到后端工序的情况下快速地进行功耗的优化,在power estimate工具中,用户甚至可以在不进行逻辑综合和物理实现的情况下对功耗进行量化的计算。


Synopsys SpyGlass 2017.12 SP2 Linux64 (Verilog检查工具)| 640 Mb

SpyGlass use many advanced algorithms and analysis techniques, provides designers with insight about their design, early in the process at RTL. It functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.
Spyglass is an important platform of Synopsys RTL verification solution that provides complete static analysis to ensure all aspects of the design are optimized before implementation such as Lint, CDC, Power, Constraints, DFT/DSM etc.

Language: English
Operating Systems: RHEL 5.x-7.x 64Bit

Synopsys Custom Compiler 2017.12-SP1 Linux64

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Custom Compiler将定制设计任务时间由数天缩短至数小时,消弭了FinFET的生产力差距。为了将FinFET版图生产力提升到新的高度,Synopsys采用了新颖的定制设计方法,即开发视觉辅助自动化技术,从而提高普通设计任务的速度,降低迭代次数并支持复用。通过与行业领先的客户的密切合作,Custom Compiler已经在最先进的节点上进行生产工作,并通过行业领先的工厂获得了FinFET工艺技术的支持(参看今天新闻辅稿)。许多Custom Compiler用户将于今天在圣塔克拉拉会议中心开幕的硅谷Synopsys用户群大会上分享各自的经验。

视觉辅助自动化

Custom Compiler Assistants可提高生产力,它利用版图设计人员所熟悉的图形使用模式,无需编写复杂代码和约束条件,无需额外设置,Custom Compiler即可自动处理日常和重复性工作。Custom Compiler提供了四种辅助功能:Layout、In-Design、Template和Co-Design。

· Layout Assistants通过可视觉引导的自动布局及绕线提高了设计速度。该款绕线器是连接FinFET阵列和大型M型晶体管的首选。它可以自动克隆连接并创建 pin tap。用户仅使用鼠标就可引导绕线器,由Custom Compiler自动完成绕线细节。设计人员可以使用创新方法进行器件布局。该方法允许用户持续优化,在提供布局选择的同时使版图设计人员能够完全控制结果,无需预先输入任何文本约束条件。

· In-Design Assistants通过在验收验证前捕捉物理和电气错误,降低成本高昂的设计迭代次数。Custom Compiler包括速度极快并始终保持激活状态的嵌入式设计规则检查(DRC)引擎。另外,Custom Compiler还内建电迁移检查以及电阻和电容提取引擎。与其他“电感知”工具不同,Custom Compiler的提取功能基于Synopsys黄金标准的StarRC™内核。

· Template Assistants帮助设计人员复用现有知识累积,使之轻松将之前的版图决策用于新的设计。Template Assistants实际上可以通过Layout Assistants的布局器和绕线器从已完成的工作中自动学习知识。Template Assistants智能识别与先前完成的电路类似的电路,并支持用户将相同的版图和绕线模式当作模板用于新的电路。Custom Compiler出厂时加载了一套内置常用电路模板,如电流镜、电平位移器和差分对。

· Co-Design Assistants将IC Compiler™和Custom Compiler合并为统一的定制和数字实现解决方案。用户可以自由地在Custom Compiler与 IC Compiler之间来回切换,使用各自的指令持续完成自己的设计。利用Co-Design Assistants,IC Compiler用户可以在任何实现阶段对其数字设计执行全定制编辑。同样地,Custom Compiler用户可以利用IC Compiler在自己的定制设计中实施数字实现流程。Co-Design Assistants的无损多次往返功能可确保跨所有数字和定制数据库同步所有变更。

Custom Compiler基于行业标准Open Access数据库,提供包括电路图、模拟分析与版图的开放环境。Custom Compiler结合Synopsys的电路仿真、物理验证以及数字实施工具,提供了一种全面的定制设计解决方案。


Synopsys Custom Compiler 2017.12-SP1 Linux64 (定制设计解决方案)| 2.757 Gb

Custom Compiler is Synopsys’ full-custom solution that features the pioneering visually-assisted automation flow that speeds up custom design tasks, reduces iterations and enables reuse. Tuned for rapid implementation of FinFET custom designs, it shortens the time it takes to complete FinFET custom design tasks from days to hours. Its visually-assisted automation flow leverages the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.

Highlights
– Template Assistants help designers reuse existing custom layout know-how
– In-Design Assistants reduce iterations with native design rule checks and parasitic extraction
– Layout Assistants speed up layout tasks with user-guided placement and routing
– Co-Design Assistants unify custom and digital flow to accelerate mixed-signal IC design

Language: English
Operating Systems: RHEL 5.x-7.x 64Bit