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Mentor Graphics Visual Elite 4.4.1 R2012.09 Win/Linux

Visual Elite图像产品具有Advanced SystemC建模及分析功能。该工具的最新版本包括原始SystemC构造,允许用户在SystemC内建模并验证设计。 该工具的HDL版本可帮助门级设计师们学习用Verilog和VHDL设计。最新版本的Visual Elite可帮助硬件设计师们和C/C++编程者迅速使用SystemC语言创建系统。Visual Elite 允许用户熟悉语言后,使用预建图形模块创建系统并自行创建文本模块。 该工具的浏览器便于用户查看硬件和软件设计架构的相关性,这对使用C/C++编写代码时是非常有用的,也有助于查看问题。浏览器和文件编辑器在建模和仿真时是同步并有效的,用于查看设计架构和执行情况。

Mentor Graphics Visual Elite 4.4.1.R2012.09 Win/Linux (建模及分析) | 350 Mb
Visual Elite is built upon a strong HDL implementation infrastructure while offering the most advanced electronic system-level (ESL) and transaction level modeling (TLM) concepts and mechanisms.
SystemC TLM blocks, VHDL and Verilog Blocks, and even software blocks in embedded systems all need to be managed and integrated into one system that should be verified and taken gradually into implementation.
Visual Elite offers a variety of languages and design entry methods allowing the user to select the best suited approach for their modeling needs. Visual Elite supports both text-based and graphical entry, including block diagrams, state diagrams and connectivity tables. Designers can use VHDL, Verilog, SystemC or any combination of these to design and build products.
Visual Elite allows distributed design teams efficient control and management of the entire design process. Built-in documentation and reuse features, such as text-to-graphics transformation, simplify design management. The design infrastructure for data and project management enables team leaders to enforce a consistent design flow and methodology. The documentation capability enables chip architects and designers to share ideas and design requirements, including hierarchical views within HTML, and links into Microsoft OLE and FrameMaker.
Visual Elite can link with existing mixed-language designs and offer cross language model distribution, including mapping SystemC RTL into HDL. Model generation can be tailored to various SystemC and HDL synthesis tools and allows single source modeling. Visual Elite supports custom modules from tools such as SPW, Matlab, and popular FPGA core libraries.

Language: English
Operating Systems: Windows 7/8.x/RHEL 4.x-5.x

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