ESP是常用的定制设计全功能验证，如嵌入式存储器，自定义宏，标准单元和I / O单元库的一个形式等效性检查工具。它是用来确保两个设计表示在功能上是等价的。这些设计可以被描述为Verilog Models，RTL，RTL, UDP’s, gates, 或者 SPICE netlist views。
ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries. It is used to ensure that two design representations are functionally equivalent. These designs may be described as behavioral Verilog Models, RTL, UDP’s, gates, or SPICE netlist views.
With the increasing complexity and importance of memories in modern ICs, there is a clear need for new tools and techniques for the design and verification of embedded memory blocks. ESP-CV puts formal technology into the memory designer’s hands raising their confidence in the quality of the design, simplifying the testing process and increasing the overall verification productivity.
- Fast and broad coverage quickly finds bugs yielding higher quality
- Supports new device technologies through Device Model Simulation and increases productivity
- Directly verifies the SPICE netlist, eliminating the need for gate-level abstraction
Operating Systems: RedHat Entrprise Linux 4.x-5.x