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Concept GateVision 6.9.2 Win/Linux

GateVision – 高性能网表调试和网表查看
GateVision®PRO是Concept Engineering的第三代图形门级网表分析仪和网表查看器。请查看演示视频:基本功能。 GateVision PRO完全改写为在现代32/64位平台上运行,可为设计师提供直观的设计导航,网表查看,波形查看,逻辑圆锥提取,网表调试和设计文档的交互式逻辑圆锥查看。

超快速网表查看器 – GateVision PRO是一款超快速和超大容量门级网表调试器和网表查看器,可读取和处理最大的Verilog网表,EDIF网表和LEF / DEF网表。阅读Verilog,EDIF和LEF / DEF网表,GateVision PRO可以无缝地融入任何设计环境。动态生成原理图,直观的图形用户界面让设计人员可以逐步轻松地浏览最大的网表文件。

GateVision屏幕转储
用于Verilog,EDIF和LEF / DEF的极高性能网表查看器
基于Tcl的UserWare API – 用于高级定制
32/64位数据库处理当今最大的SoC,ASIC和FPGA
集成波形浏览器(加速VCD查看器)
可定制的路径提取引擎找到关键路径
锥视图显示关键区域的示意图片段
直观的GUI,易于使用
API – 基于tcl的UserWare API提供对全新32/64位数据库的完全访问,以实现高度灵活的定制。设计人员可以扩展GateVison PRO的功能,以满足项目的直接需求,例如增加电子规则检查(ERC),报告和文档功能。该API还允许GateVison PRO与不同的设计流程和第三方工具紧密集成。

波形查看器和信号跟踪 – GateVision PRO带有完全集成的波形查看器,并支持源代码,原理图和波形窗口中的交互式信号跟踪。 GateVision PRO将VCD模拟数据编译成其自己的高速格式,用于加速波形浏览和信号跟踪。

GateVision屏幕转储

32/64位 – 即使是当今最大,最复杂的当今要求苛刻的ASIC,SoC和FPGA,利用日益强大的64位平台,Intel Xeon,Intel Core,AMD Opteron和AMD Phenom,GateVision PRO也可以快速有效地运行。底层数据库已经完全重新设计为32/64位操作。

逻辑锥 – GateVision PRO逻辑锥视图在原理图片段中提供了交互式导航,该部分是最相关的电路。通过完整的设计层次结构,可以扩展和减少信号路径跟踪。

路径提取和Verilog仿真 – 可定制的路径提取引擎可以自动识别和提取设计中的关键路径。这些可以在不同视图中进行探索和交叉探测,以减少调试周期的复杂性和时间。路径片段可以作为Verilog网表导出用于关键路径Verilog仿真。

GateVision PRO屏幕转储

GUI – 直观的GUI提供了许多功能,包括上下文敏感菜单和多个视图。强大的搜索工具可以快速访问设计中的任何对象或对象组,并将结果存储在结果列表中。列出的对象可以突出显示或移动到逻辑圆锥窗口中。

调试视图 – 内置于GateVision Pro中有各种视图选项,包括原理图视图,原理图分数视图,源代码视图,层次树视图,波形视图,时钟域视图和对象搜索视图。通过这些以及通过视图间的交叉探测,很容易深入了解正在调试的设备并改进调试过程。


Concept GateVision v6.8.12/6.9.2 | 102.8 mb

GateVision – High Performance Netlist Debugging and Netlist Viewing
GateVision® PRO is the third generation of graphical gate-level netlist analyzers and netlist viewers from Concept Engineering. Please check out the Demo Video: Basic Features. Completely rewritten to run on modern 32/64bit platforms, GateVision PRO provides the designer of even the largest chips and SoCs with intuitive design navigation, netlist viewing, waveform viewing, logic cone extraction, interactive logic cone viewing for netlist debugging and design documentation.

Ultra Fast Netlist Viewer — GateVision PRO is an ultra fast and extreme capacity gate-level netlist debugger and netlist viewer reading and processing even the largest Verilog netlists, EDIF netlists and LEF/DEF netlists. Reading Verilog, EDIF and LEF/DEF netlists, GateVision PRO fits seamlessly into any design environment. Schematics are generated on the fly and the intuitive GUI lets the designer incrementally and easily navigate through the largest netlist files.

GateVision Screen Dump
Extreme performance netlist viewer for Verilog, EDIF, and LEF/DEF
Tcl based UserWare API — for advanced customization
32/64 bit database handles today′s largest SoCs, ASICs and FPGAs
Integrated Waveform Browser (accelerated VCD viewer)
Customizable path extraction engine finds critical paths
Cone view displays schematic fragments of critical areas
Intuitive GUI for ease of use
API — a tcl based UserWare API provides full access to the new 32/64-bit based database, for highly flexible customization. The designer can extend the functionality of GateVison PRO to meet the immediate needs of the project, adding, for example, electrical rule checking (ERC), report and documentation functions. The API also allows GateVison PRO to be closely integrated with different design flows and third party tools.

Waveform Viewer and Signal Tracing — GateVision PRO comes with a fully integrated waveform viewer and with support for interactive signal tracing in the source code, schematic view and waveform window. GateVision PRO compiles VCD simulation data into its own high-speed format for accelerated waveform browsing and signal tracing.

GateVision Screen Dump

32/64 Bit — exploiting the increasing powerful 64 bit platforms, Intel Xeon, Intel Core, AMD Opteron and AMD Phenom, GateVision PRO runs quickly and efficiently, even for the largest and most complex of today′s demanding ASICs, SoCs and FPGAs. The underlying database has been completely redesigned for 32/64-bit operation.

Logic cone — the GateVision PRO logic cone view provides interactive navigation within a schematic fragment, that portion of the circuit that is most relevant. This can be extended and reduced for signal path tracing through the complete design hierarchy.

Path extraction and Verilog Simulation — The customizable path extraction engine can automatically identify and extract critical paths in a design. These can be explored and cross-probed in different views to reduce both the complexity and time of the debug cycle. Path fragments can be exported as Verilog netlists for critical path Verilog simulation.

GateVision PRO Screen Dump

GUI — the intuitive GUI provides a host of facilities including context sensitive menus and multiple views. A powerful search tool provides quick access to any object or group of objects in a design, with the results stored in a result list. Listed objects can be highlighted or moved into the logic cone window.

Debugging Views — Built into GateVision Pro are a variety of view options, including schematic view, schematic fraction view, source code view, hierarchy tree view, waveform view, clock domain view, and object search view. Through these, and through cross-probing between views, it is easy to gain a deeper understanding of the device being debugged and to improve the debugging process.

Language: English
Operating Systems: Windows 7/8.x/10.x

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