Synplify FPGA包含可选Synplify Pro和Synplify Premier FPGA综合工具。
Synopsys Synplify FPGA设计软件提供了一个高品质，高性能和易于使用的FPGA实现和调试环境。采用Synopsys的FPGA工具套件增益设计师快速进入超结果为复杂的FPGA，面积优化成本和降低功耗，自动化软错误缓解，分层设计能力和多FPGA厂商的支持。该的Synplify Pro和Synplify Premier FPGA设计工具，通过提供链接到高性能功能验证与VCS仿真和集成Synphony模型编译器的信号处理硬件的高层次综合提供额外的价值。
许多设计和验证团队越来越倾向于使用基于 FPGA 的原型验证，以便使产品及时进入市场。 基于 FPGA 的 Synopsys 原型验证解决方案可以使开发者尽早进行芯片制造前的嵌入式软件开发和软硬件协同设计，从而缩短上市时间并降低昂贵的器件改版费用。 同时，我们紧密集成且易于使用的HAPS硬件和软件工具套件可大幅加快从单个 IP 模块到处理器子系统再到整个SoC的软件开发、软硬件集成和系统验证。
Synplify Premier solution is the industry’s most productive FPGA implementation and debug environment. It includes all the features of Synplify Pro and additionally provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes.
The Synplify Premier software delivers fast turnaround time capabilities and feedback for users seeking to quickly implement the design on the board or to tune their design projects prior to final implementation. It addresses the most challenging aspects of FPGA design including timing closure and has the ability to perform graph-based physical synthesis for more accurate upfront timing prediction. It provides flows for fast logic verification and RT-Level debug. Under the hood, it contains optimization techniques that enhance DSP, IP and embedded design results. For ASIC prototypers, it delivers ASIC design file and DesignWare compatibility as well as tight integration with the Confirma Rapid Prototyping platform and FPGA vendor back-end tools as well as vendor embedded tools including Altera SoPC Builder and Xilinx EDK.
The Synplify Premier product offers FPGA Designers and ASIC Prototypers, targeting single FPGA-based prototypes, with the most efficient method of design implementation and debug. The Synplify Premier software provides in-system verification of FPGAs, dramatically accelerates the debug process, and provides a rapid and incremental method for finding elusive design problems.
The Synplify Premier software advantages include:
* technology and vendor independence
* in-system debug
* fast timing closure
* RTL analysis
* DSP-friendly synthesis algorithms
* superior Quality of Results (QoR)
Operating Systems: Windows 7/8.x/10.x/RHEL 6.6+, 7.x/SLES 11.x and 12.x