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Synopsys Library Compiler 2018.06 SP1 Linux64

Synopsys Library Compiler工具可以从文本中读取ASIC库类型并将其编译为内部数据库(.db格式)或VHDL库。
编译的数据库支持synthesis工具,VHDL库支持VHDL仿真工具。
Library Compiler的作用是生成两种类型的库,支持Synopsys合成和模拟产品。这两种类型的库是
Synthesis库
综合库由技术库,物理库和符号库组成,其中包含描述ASIC组件所需的信息类型:技术和物理特性以及原理图符号。
•技术库包含有关ASIC库中每个组件的特征和功能的信息。存储在技术库中的信息包括区域,时序,功能等。 Synopsys设计工具使用此信息做出综合决策。
•符号库包含有关表示每个ASIC组件的原理图符号的信息,以及有关特殊符号的信息,例如页面边框和表外连接器。然后,您可以使用Design Analyzer工具
•生成设计原理图
•在计算机屏幕上显示原理图
•使用PostScript绘图仪或打印机绘制设计
•有关物理库的信息,请参阅库编译器物理库
VHDL模拟ASCII库
Library Compiler可以生成VHDL库,其中包含模拟所需的时序和功能信息。


Synopsys Library Compiler 2018.06 SP1 Linux64 (库编译工具)| 517 Mb

The Library Compiler tool from Synopsys reads the description of an ASIC library from a text file and compiles the description into either an internal database (.db format) or into VHDL libraries.
The compiled database supports synthesis tools. The VHDL libraries support VHDL simulation tools.
The role of Library Compiler is to generate two types of libraries that support Synopsys synthesis and simulation products. The two types of libraries are
Synthesis Libraries
The synthesis libraries consist of the technology libraries, physical libraries, and symbol libraries that contain the types of information required to describe ASIC components: technical and physical characteristics and schematic symbols.
• Technology libraries contain information about the characteristics and functions of each component in an ASIC library. Information stored in the technology libraries consists of area, timing, function, and so on. The Synopsys design tools use this information to make synthesis decisions.
• Symbol libraries contain information about the schematic symbols that represent each ASIC component, as well as information about special symbols, such as page borders and off-sheet connectors. Using the Design Analyzer tool, you can then
• Generate schematics of designs
• Display the schematic on the computer screen
• Draw the designs, using your PostScript plotter or printer
• For information about physical libraries, see the Library Compiler Physical Libraries
VHDL Simulation ASCII Libraries
Library Compiler can generate VHDL libraries that contain the timing and functional information needed for simulation.

Language: English
Operating Systems:RHEL 6.x-7.x 64Bit

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