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Cadence IC 06.17.721 Virtuoso Linux

全球电子设计创新领导者Cadence Design Systems公司发布了更新的(06.17.721_Hotfix)IC 06.17.700 Virtuoso。 Virtuoso工具套件有助于集成电路的全定制设计。该套件提供各种设计和验证工具,可为不同的设计要求提供完整的前端到后端解决方案,例如全定制集成电路和数字集成电路。

关于Cadence Virtuoso系统设计平台。
Cadence Virtuoso系统设计平台是一个基于系统的整体解决方案,提供从单一原理图驱动IC和封装的LVS清洁布局的功能。有两个关键流程:实施和分析。

实现流程用于在Virtuoso原理图编辑器中创建IC封装原理图,然后将原理图数据传输到Cadence SiP布局以布局物理设计。此外,该流程还提供生成和验证库零件,输出物料清单(BOM)以及执行布局与原理图(LVS)检查的功能。

无论布局设计状态如何,分析流程都用于提取和模拟系统的任何部分(IC-package-PCB)。此外,该流程还能够自动生成PCB和IC封装布局的原理图,将IC封装的实例绑定到ICschematic或模型,并使用Virtuoso ADE ProductSuite和Spectre多模仿真构建测试平台以模拟系统接口。从PCB和IC封装布局中提取的Cadence Sigrity模型会自动拼接到生成的原理图中。

IC 06.17.700附带的独立软件:
– Virtuoso Power System L (IC6.1.7)
– Voltus-Fi Custom Power Integrity Solution XL IC6.1.7
– Dracula Design Rule Checker (4.9)
– Dracula Layout Vs. Schematic Verifier (4.9)
– Dracula Parasitic Extractor(4.9)
– Dracula Physical Verification Suite(4.9)
– Dracula Physical Verification and Extraction Suite (4.9)
– Virtuoso Chip Assembly Router (11.3)


Cadence IC 06.17.700 With 06.17.721_Hotfix Virtuoso (系统设计平台) | 4.2 Gb

Cadence Design Systems, Inc., the leader in global electronic design innovation, has released an updated (06.17.721_Hotfix) IC 06.17.700 Virtuoso. The Virtuoso suite of tools facilitates the full-custom design of integrated circuits. The suite offers a wide range of design and verification tools that provide complete front-to-back solutions for varying design requirements, such as full-custom integrated circuits and digital integrated circuits.

About Cadence Virtuoso System Design Platform.
The Cadence Virtuoso System Design Platform is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean layout of ICs and packages from a single schematic. There are two key flows: implementation and analysis.

The implementation flow is used to create an IC package schematic in Virtuoso Schematic Editor and then transfer the schematic data to Cadence SiP Layout to layout the physical design. In addition, this flow offers the capability to generate and verify library parts, output a bill of materials (BOM), and perform layout versus schematic (LVS) checking.

The analysis flow is used to extract and simulate any portion of the system (IC-package-PCB) regardless of the layout design status. Moreover, this flow offers the capability to automatically generate schematics for the PCB and IC package layouts, bind the instances of the IC package to the ICschematic or models, and build testbenches to simulate the system using the Virtuoso ADE ProductSuite plus Spectre Multi-Mode Simulation interface. Cadence Sigrity models extracted from the PCB and IC package layouts get automatically stitched into the generated schematic.

Standalone Software Shipped with IC 06.17.700:
– Virtuoso Power System L (IC6.1.7)
– Voltus-Fi Custom Power Integrity Solution XL IC6.1.7
– Dracula Design Rule Checker (4.9)
– Dracula Layout Vs. Schematic Verifier (4.9)
– Dracula Parasitic Extractor(4.9)
– Dracula Physical Verification Suite(4.9)
– Dracula Physical Verification and Extraction Suite (4.9)
– Virtuoso Chip Assembly Router (11.3)

Language: English
Operating Systems: RHEL 5.x-7.x

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