Questa Ultra验证平台支持将设计验证从TLM加速到RTL再到片上应用的验证过程。所以，它可帮助用户将高效验证技术用于复杂的设计。Questa Ultra验证平台集成了仿真和相关技术，用以处理智能测试平台自动化、低功耗验证和验证管理等问题。QuestaUltra验证平台也与用于跨时钟域（CDC）和形式验证的专业化技术紧密结合，解决通常难以覆盖到的设计问题。
Questa Ultra delivers a 10X improvement in time to coverage. Integrating simulation with intelligent testbench automation, Questa Ultra eliminates redundancy in randomized testbenches, reducing the amount of time and workstation resources required to hit coverage targets. Questa Ultra further extends the Questa Prime version to include UPF (unified power format) support for power aware simulation and verification, along with integrated intelligent testbench automation.
Questa Ultra includes the Questa inFact and Questa Core/Prime application software.
New Core/Prime Features
The following new features are available in the 10.7 release series. VM indicates that the feature is contained in the Verification Management Tools and PA indicates Power Aware Simulation
• Improved VHDL performance – memories, clocks, composites
• Improved SystemVerilog performance, stability, support
• Gate Level add_seq_delay and other optimizations
• Improved access write performance
• Early access support of IEEE 1735 version 2 cryptography
• Improved coverage adaptive exclusions, reporting consistency
• Power Aware performance, new reports, more UPF3.0 support (PA)
• Deprecated old -novopt flow, option to be removed in next release
New inFact Features
The release v10.6a contains the following new features:
Packed Array Enhancements
inFact IDE and TBI supports:
• Use of a meta_action with an explicit bit-width that can be accessed as a packed array within a foreach constraint, similar to bit vector in System Verilog. For more information, see Array of meta_actions in Questa inFact User’s Manual.
• Use of System Verilog built-in function $countones().The countones function is a constraint expression that counts the number of one-bits in the scalar value.
Testbench Import (TBI) Enhancements
New TBI switches added for controlling the unrolling of arrays in infact cmd import_testbench:
• [-disable_unroll_array struct-type | struct-type::array]
• [-enable_unroll_array struct-type | struct-type::array]
QSA Batch Mode Enhancements
• QSA Batch Mode is an operational mode that allows you analyze and get the results of analysis without invoking the GUI.You need to specify an input CSV file for QSA
arguments and get results from the output CSV file. For more information, see QSA in Batch Mode in
• New QSA command line arguments added: -batch, -analysis_spec, -o, and -v. For more information, see QSA Command Line Arguments in Questa inFact User’s Manual.
QSA GUI Mode Enhancements
• Added File Menu options in QSA GUI mode. The File selection from the main menu lets you open configuration file in CSV format, save the configuration file, save the
result in a .out file, and exit QSA.
• QSA Source Viewer – you can view SystemVerilog source code directly from the QSA Interface.You can double-click the variable or constraint to open the source code with
the highlighted variable or constraint in the source code.
Operating Systems: RHEL 6.x-7.x