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Synopsys Formality 2018.06 SP1 Linux64

Synopsys Formality是一种等效性检测工具,采用形式验证的技术来判断一个设计的两个版本在功能上是否等效。等效性检测是一种静态分析方法,无需测试向量即可快速而全面的完成验证。Formality具有一个流程化的图形界面和先进的调试功能,令设计者可以很快地检测出设计中地错误并将之隔离,这一功能可以大大缩短得到验证结果所需的时间。Formality业界领先的功能和性能使之成为设计团队的首选产品。与传统的仿真或是竞争对手的工具相比,Formality具有很多优点。
● 通过完备的验证覆盖将流片失败的可能性降到最低
● 对一个几百万门的设计进行验证以分钟记数,加快了产品上市时间
● 降低了工具设置的需求并提供快速错误隔离的功能,显著的缩短了传统的等效性检测的周期
● 工具简单易学,无需艰苦的培训,最大化的方便工程师的使用
● 提供了为业界所证实的先进功能,能充分利用现有的硬件资源


Synopsys Formality 2018.06 SP1 Linux64 (等效性检测工具) | 460 Mb

The Formality Equivalence Checker uses formal techniques to prove or disprove equivalence between two versions of the same design. Equivalence checking is a type of static analysis that verifies large designs both quickly and completely without the use of test vectors. The high performance and reduced risk of static analysis has led to the rapid adoption of equivalence checking within leading verification flows, making it a must for all competitive design processes.

Key Benefits

  • Exhaustive verification, without test vectors, in a fraction of the time consumed by traditional dynamic techniques
  • Proves functional correctness of register retiming, complex datapath, ECO, and low power implementations–from within a single product
  • Reduces manual setup with verified automated setup guidance
  • Verifies full-custom and memory designs when including ESP technology

Design Challenges
Verification engineers often have limited knowledge of logic transformations that can occur during a designs implementation, making the optimal setup of an equivalence checking tool difficult to achieve. Missing or incorrect setup information prevents peak verification performance. In some cases, EC tools may produce a non-equivalent result when the designs are indeed equivalent (a false difference). Even when an engineer is aware of the numerous implementation optimizations, manual setup can be time consuming and error prone. These issues are exacerbated as new and unique design challenges drive further design optimizations.

Solution
Formality supports the use of guided setup files and the Synopsys V-SDC verification setup standard to automatically account for the most common design transformations, such as name and register changes. Every gate continues to be verified with Formality’s trusted technology, and you gain the performance and first-pass completion benefits of correct-by-construction setup.

Language: English
Operating Systems: RHEL 5.x-7.x 64Bit

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