The Formality Equivalence Checker uses formal techniques to prove or disprove equivalence between two versions of the same design. Equivalence checking is a type of static analysis that verifies large designs both quickly and completely without the use of test vectors. The high performance and reduced risk of static analysis has led to the rapid adoption of equivalence checking within leading verification flows, making it a must for all competitive design processes.
- Exhaustive verification, without test vectors, in a fraction of the time consumed by traditional dynamic techniques
- Proves functional correctness of register retiming, complex datapath, ECO, and low power implementations–from within a single product
- Reduces manual setup with verified automated setup guidance
- Verifies full-custom and memory designs when including ESP technology
Verification engineers often have limited knowledge of logic transformations that can occur during a designs implementation, making the optimal setup of an equivalence checking tool difficult to achieve. Missing or incorrect setup information prevents peak verification performance. In some cases, EC tools may produce a non-equivalent result when the designs are indeed equivalent (a false difference). Even when an engineer is aware of the numerous implementation optimizations, manual setup can be time consuming and error prone. These issues are exacerbated as new and unique design challenges drive further design optimizations.
Formality supports the use of guided setup files and the Synopsys V-SDC verification setup standard to automatically account for the most common design transformations, such as name and register changes. Every gate continues to be verified with Formality’s trusted technology, and you gain the performance and first-pass completion benefits of correct-by-construction setup.
Operating Systems: RHEL 5.x-7.x 64Bit