网络万千资源
服务广大工程师

Synopsys Verdi 2017.03 SP2 Linux64

Verdi自动化侦错系统是先进的开放平台拥有强大的数位侦错技术,可以帮助你理解复杂的和不熟悉的设计问题,自动化困难和繁琐的侦错过程、和统一多样化和复杂化的设计环境。

减少一半的侦错时间
Verdi 自动化侦错系统让用户能专注在更有价值的设计工作上,通过以下的独特技术,基本上可减少至少百分之五十以上的侦错时间:

  • 使用独家的行为分析(Behavior Analysis)技术自动追踪设计行为
  • 以各种不同且功能强大的窗口提取并呈现相关逻辑电路
  • 展现逻辑设计(logic design)、低功耗设计(Power Intent)、断言(assertion)、以及testbench运作下的交互关系

完整的侦错系统
Verdi 自动化侦错系统包含了侦错系统所需的各项侦错相关技术与功能。此外,Verdi系统更结合了先进的侦错技术,以支持更广泛的设计语言和方法。

核心功能
Verdi自动化侦错系统提供了下列基本的侦错功能:

  • 具有完整功能的波型显示器,使您可以随时显示和分析活动
  • 强大的波形比较引擎,使您可以隔离不同快速信号数据库(FSDB)间的差异
  • 程序代码浏览器(Source Code Browser)让您可轻易的穿梭于不同程序代码及设计层级(Hierarchy)之间
  • 便利的电路图、区块图、局部电路图让您可用熟悉的符号来追踪电路和连线
  • 直觉的气泡图让您轻易了解有限状态机的运作

先进功能
Verdi 自动化侦错系统涵盖了下列先进的侦错功能:

  • 自动追踪信号活动,根据强大的行为分析技术,您可以快速追踪跨越多个频率周期的信号活动
  • 时间流程图(Temporal flow view)提供了结合时间与电路结构的呈现方式,让您快速了解其中的因果关系
  • 以Transaction为基础的侦错,其中包含了对Transaction和Message的广泛支持。使用者可在更高层的概念图中进行侦错与分析
  • 以断言(Assertion)为基础的侦错,其中内建的便利功能更能帮助用户由断言错误发生点主动追踪至相关的程序代码
  • 针对SystemVerilog Testbench的侦错,其中包含了:
    • 完整的源代码支持SystemVerilog测试平台(SVTB)和数据库,包括通用验证方法学(UVM),以确保测试平台代码的复用性和互操作性
    • 能帮助用户快速了解Testbench程序代码的专业窗口,所提供的功能包括以宣告为基础(declaration-based)的程序浏览,以及针对class间相互与继承关系的了解及追踪
    • 内置的信息记录和UVM transaction自动记录的能力,配合先进的可视化技术,提供后处理的验证环境中测试平台活动的完整画面
    • 你可以使用全功能的交互式仿真控制来单步进入复杂的testbench代码,作更细节地分析。
    • UVM的调试界面允许使用者通过特定的UVM属性,比如resources、factory、phase和sequence等来分析验证结果。
    • 事物级的调试界面是基于扩展的FSDB,并且可以保存事物和相关数据。

Synopsys Verdi 2017.03 SP2 Linux64 (FPGA验证工具) | 1920 Mb

Verdi Automated Debug System is the centerpiece of the Verdi SoC Debug Platform and enables comprehensive debug for all design and verification flows. It includes powerful technology that helps you comprehend complex and unfamiliar design behavior, automate difficult and tedious debug processes and unify diverse and complicated design environments.
Cut Debug Time in Half
The Verdi® system lets you focus on tasks that add more value to your designs, by cutting your debug time, by typically over 50%. These time savings are made possible by unique technology that:

  • Automates behavior tracing using unique behavior analysis technology
  • Extracts, isolates, and displays pertinent logic in flexible and powerful design views
  • Reveals the operation of and interaction between the design, assertions, and testbench

Complete Debug System
The Verdi automated debug system incorporates all of the technology and capabilities you would expect in a debug system. In addition, the Verdi system combines advanced debug features with support for a broad range of languages and methodologies.

Core Features
The Verdi system provides the following fundamental debug features:

  • Full-featured waveform viewer enables you to display and analyze activity over time
  • Powerful waveform comparison engine allows you to isolate differences between fast signal database (FSDB) files
  • Source code browser enables you to easily traverse between source code and hierarchy
  • Flexible schematics and block diagrams give you the ability to display logic and connectivity using familiar symbols
  • Intuitive bubble diagrams help you to reveal the operation of finite state machines


Advanced Features

The Verdi system also includes the following advanced debug features:

  • Automatic tracing of signal activity enables quick trace activity across many clock cycles with powerful behavior analysis technology
  • Temporal flow views provide a combined display of time and structure to help you rapidly understand cause and-effect relationships
  • Transaction-based debug with flexible transaction and message support for debug and analyzing designs at higher levels of abstraction
  • Assertion-based debug with built-in support for assertions facilitates quick traversal from assertion failure to related design activity
  • SystemVerilog Testbench debug with:
    • Full source code support for SystemVerilog Testbench (SVTB) and libraries, including Universal Verification Methodology (UVM), to ensure reusability and interoperability of testbench code
    • Specialized views that help you understand testbench code, including declaration-based hierarchy browsing and navigation, class inheritance and relationship comprehension, and tracing
    • Built-in message logging and automated UVM transaction recording capabilities, coupled with advanced visualization techniques, give you a complete picture of testbench activity in the post-simulation verification environment
    • Full-featured interactive simulation control allows you to step through complex testbench code for more detailed analysis
    • UVM-aware debug views allow users to explore verification results from specific UVM aspects like resources, factory, phase and sequence
    • Transaction-level debug views are based on extended FSDB and support new transaction and relation data recording

Language: English/
Operating Systems: RHEL 5.x-7.x 64Bit

Download 百度云 (VIP用户下载区)

此版本资源不提供下载地址,如有兴趣请通过右侧联系方式来咨询我们,评论区留言一概不复!
It is not allowed for download directly,contact us if interesting.

1.请使用IDM下载工具下载,WinRAR 5.x解压缩,解压密码:www.poqsoft.com;
2.本站所有VIP会员文件经卡巴斯基杀毒软件查杀,绝不带任何后门病毒;
3.不要为了省顿饭钱浪费大量时间,不要为了贪图便宜而被骗,专业技术绝对有保障。

赞(0) 打赏
未经允许不得转载:资源交互平台 » Synopsys Verdi 2017.03 SP2 Linux64
分享到: 更多 (0)

评论 抢沙发

评论前必须登录!

 

觉得文章有用就打赏一下文章作者

支付宝扫一扫打赏

微信扫一扫打赏