网络万千资源
服务广大工程师

Synopsys Identify 2018.03 Win/Linux

Synopsys Identify是一个功能强大的FPGA验证工具,让您快速查找和纠正功能设计在硬件错误的系统运行速度。该识别软件提供了高级触发功能,因此您可以准确地专注于您要查看,你选择看它设计的时候部分。最重要的是,有解释结果不需要额外的努力。您添加探头仪器的设计和直接在RTL源代码中观察结果。

该Identify RTL调试器可以让你的仪器RTL HDL后,仍然在RT级,调试直播,运行硬件实现FPGA。在确定FPGA调试软件验证设计的硬件,类似于模拟 – 只有更快,具有在系统的刺激。

该Identify RTL调试器允许您指定样本触发器,导航设计图形,并标记在RTL是作为探测器的信号。合成后,结果查看和注解到RTL源代码,HDL的Analyst®RTL查看,或第三方,波形显示器。这样可以确保从RTL到实现等价和FPGA设计正确的操作。

主要特点:

– 支持Altera公司,Microsemi的和Xilinx器件
– 有能力的仪器,并直接从RTL源代码调试先进的FPGA设计
– 高级触发创作允许所需的设计运行情况下的观察和探测电路中的特定节点
– 能见度到内部设计,同时以全速运行
– 显示调试结果的叠加的RTL源,RTL结构图顶部,或具有波形观测器
– 有选择地在调试会话期间查看多达内部节点的8个不同的组,一个确定IICE
– 综合和布局旁路选项允许的Virtex-7/6/5 FPGA的快速仪表变化
– 兼容与Synopsys验证解决方案Verdi3™和Siloti为基于FPGA的原型自动调试和知名度


Synopsys Identify 2018.03 Win/Linux (FPGA验证工具) | 210 Mb

Synopsys Identify RTL debugger allows you to instrument RTL HDL and then, still at the RT-Level, debug the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation – only much faster and with in-system stimuli.

The Identify RTL debugger allows you to designate sample triggers, navigate the design graphically, and mark signals in the RTL that are to serve as probes. After synthesis, the results are viewed and annotated onto the RTL source code, the HDL Analyst® RTL View, or third party, waveform viewer. This ensures RTL-to-implementation equivalence and correct operation of the FPGA design.

Key Features

  • Support for Altera, Microsemi and Xilinx devices
  • Ability to instrument and debug an advanced FPGA design directly from RTL source code
  • Advanced trigger creation allows the viewing of desired design operation scenarios and probe specific nodes in the circuit
  • Visibility into the internal design while operating at full speed
  • Display of debug results superimposed on top of RTL source, RTL structural view, or with a waveform viewer
  • Selectively view up to 8 distinct groups of internal nodes with a single Identify IICE during a debug session
  • Synthesis and placement bypass option allows rapid instrumentation changes of Virtex-7/6/5 FPGA
  • Compatible with Synopsys verification solutions Verdi3™ and Siloti for automated debug and visibility of FPGA-based prototypes

Download Identify Datasheet

Language: English
Operating Systems: Windows 7/8.x/RHEL 5.x-7.x

Download 百度云 (VIP用户下载区)

此版本资源不提供下载地址,如有兴趣请通过右侧联系方式来咨询我们,评论区留言一概不复!
It is not allowed for download directly,contact us if interesting.

1.请使用IDM下载工具下载,WinRAR 5.x解压缩,解压密码:www.poqsoft.com;
2.本站所有VIP会员文件经卡巴斯基杀毒软件查杀,绝不带任何后门病毒;
3.不要为了省顿饭钱浪费大量时间,不要为了贪图便宜而被骗,专业技术绝对有保障。

赞(1) 打赏
未经允许不得转载:资源交互平台 » Synopsys Identify 2018.03 Win/Linux
分享到: 更多 (0)

评论 抢沙发

评论前必须登录!

 

觉得文章有用就打赏一下文章作者

支付宝扫一扫打赏

微信扫一扫打赏