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Synopsys PrimePower 2018.06 Linux64

PrimePower是Synopsys公司的专业级数字电路的功耗评估,后来集成到PrimeTime里面。PrimePower可以仿真出数字电路的平均功耗(包含开关功耗、内部功耗和静态功耗三部分),也可以得到每个模块的功耗。另外,通过综合后的网表级仿真,得到开关活动率文件(即Saif文件)或者Dump出VCD格式的波形文件,进而得出电路在某一段时间内的功耗波形,这样可以知道电路每个时刻功耗是怎样的,根据这个功耗波形结果,来优化电路的功耗。


Synopsys PrimePower 2018.06 Linux64 (数字电路功耗评估) | 1.82 Gb

PrimePower has advantages over Design Power, said William Ruby, director of marketing for mixed-signal and low-power design at Synopsys. One is the tool’s ability to handle designs with potential capacities of up to 10 million instances. Another is PrimePower’s time-based analysis, which lets users view power dissipation as a function of time within a waveform display.

PrimePower models pattern-dependent, capacitive switching, short-circuit and static power consumption, considering instance-specific cell-state dependencies, glitches, multiple loads and nonlinear ramp effects.

To use PrimePower, an engineer first runs an HDL simulator and generates what Synopsys calls a PrimePower interface format (PIF) file. That contains switching activity and hierarchy information. The file is created by programming language interface routines provided with the tool. PIF files can be generated by Synopsys’ VCS Verilog, Cadence’s Verilog-XL and NC-Verilog and Model Technology’s ModelSim VHDL simulators.

Language: English
Operating Systems: RHEL 5.x-7.x 64Bit

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