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Mentor Graphics ModelSim 10.7b Win/Linux

Mentor Graphics ModelSim是业界最优秀的HDL语言仿真器,它提供最友好的调试环境,是唯一的单内核支持VHDL和Verilog混合仿真的仿真器。是作FPGA/ASIC设计的RTL级和门级电路仿真的首选,它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术,编译仿真速度快,编译的代码与平台无关,便于保护IP核,个性化的图形界面和用户接口,为用户加快调错提供强有力的手段。全面支持VHDL和Verilog语言的IEEE 标准,支持C/C++功能调用和调试
具有快速的仿真性能和最先进的调试能力,全面支持Windows 64位平台。
主要特点:
RTL和门级优化,本地编译结构,编译仿真速度快;
单内核VHDL和Verilog混合仿真;
源代码模版和助手,项目管理;
集成了性能分析、波形比较、代码覆盖等功能;
数据流ChaseX;
Signal Spy;
C和Tcl/Tk接口,C调试


Mentor Graphics ModelSim 10.6d/10.7b Win/Linux (HDL语言仿真器) | 738 Mb


ModelSim eases the process of finding design defects with an intelligently engineered debug environment.
The ModelSim debug environment efficiently displays design data for analysis and debug of all languages. ModelSim allows many debug and analysis capabilities to be employed post-simulation on saved results, as well as during live simulation runs.

Features

  • Multi-language, high performance simulation engine
  • Verilog, VHDL, SystemVerilog Design
  • Code Coverage
  • SystemVerilog for Design
  • Integrated debug
  • JobSpy Regression Monitor
  • Mixed HDL simulation option
  • SystemC Option
  • TCL/tk
  • 32 and 64-bit platform support — Linux, Windows

Benefits

  • High performance HDL simulation solution for FPGA & ASIC design teams
  • The best mixed-language environment and performance in the industry.
  • Intuitive GUI for efficient interactive or post-simulation debug of RTL and gate-level designs
  • Merging, ranking and reporting of code coverage for tracking verification progress
  • Sign-off support for popular ASIC libraries
  • All ModelSim products are 100% standards based. This means your investment is protected, risk is lowered, reuse is enabled, and productivity is enhanced.
  • Award-winning technical support

Language: English
Operating Systems: Windows 7/8.x/10/RHEL 6.x-7.x

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