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Concept GateVision 6.10.5 Win/Linux

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GateVision – 高性能网表调试和网表查看
GateVision®PRO是Concept Engineering的第三代图形门级网表分析仪和网表查看器。请查看演示视频:基本功能。 GateVision PRO完全改写为在现代32/64位平台上运行,可为设计师提供直观的设计导航,网表查看,波形查看,逻辑圆锥提取,网表调试和设计文档的交互式逻辑圆锥查看。

超快速网表查看器 – GateVision PRO是一款超快速和超大容量门级网表调试器和网表查看器,可读取和处理最大的Verilog网表,EDIF网表和LEF / DEF网表。阅读Verilog,EDIF和LEF / DEF网表,GateVision PRO可以无缝地融入任何设计环境。动态生成原理图,直观的图形用户界面让设计人员可以逐步轻松地浏览最大的网表文件。

GateVision屏幕转储
用于Verilog,EDIF和LEF / DEF的极高性能网表查看器
基于Tcl的UserWare API – 用于高级定制
32/64位数据库处理当今最大的SoC,ASIC和FPGA
集成波形浏览器(加速VCD查看器)
可定制的路径提取引擎找到关键路径
锥视图显示关键区域的示意图片段
直观的GUI,易于使用
API – 基于tcl的UserWare API提供对全新32/64位数据库的完全访问,以实现高度灵活的定制。设计人员可以扩展GateVison PRO的功能,以满足项目的直接需求,例如增加电子规则检查(ERC),报告和文档功能。该API还允许GateVison PRO与不同的设计流程和第三方工具紧密集成。

波形查看器和信号跟踪 – GateVision PRO带有完全集成的波形查看器,并支持源代码,原理图和波形窗口中的交互式信号跟踪。 GateVision PRO将VCD模拟数据编译成其自己的高速格式,用于加速波形浏览和信号跟踪。

GateVision屏幕转储

32/64位 – 即使是当今最大,最复杂的当今要求苛刻的ASIC,SoC和FPGA,利用日益强大的64位平台,Intel Xeon,Intel Core,AMD Opteron和AMD Phenom,GateVision PRO也可以快速有效地运行。底层数据库已经完全重新设计为32/64位操作。

逻辑锥 – GateVision PRO逻辑锥视图在原理图片段中提供了交互式导航,该部分是最相关的电路。通过完整的设计层次结构,可以扩展和减少信号路径跟踪。

路径提取和Verilog仿真 – 可定制的路径提取引擎可以自动识别和提取设计中的关键路径。这些可以在不同视图中进行探索和交叉探测,以减少调试周期的复杂性和时间。路径片段可以作为Verilog网表导出用于关键路径Verilog仿真。

GateVision PRO屏幕转储

GUI – 直观的GUI提供了许多功能,包括上下文敏感菜单和多个视图。强大的搜索工具可以快速访问设计中的任何对象或对象组,并将结果存储在结果列表中。列出的对象可以突出显示或移动到逻辑圆锥窗口中。

调试视图 – 内置于GateVision Pro中有各种视图选项,包括原理图视图,原理图分数视图,源代码视图,层次树视图,波形视图,时钟域视图和对象搜索视图。通过这些以及通过视图间的交叉探测,很容易深入了解正在调试的设备并改进调试过程。


Concept GateVision v6.10.5/6.9.12/6.8.12 | 102.8 mb

GateVision – High Performance Netlist Debugging and Netlist Viewing
GateVision® PRO is the third generation of graphical gate-level netlist analyzers and netlist viewers from Concept Engineering. Please check out the Demo Video: Basic Features. Completely rewritten to run on modern 32/64bit platforms, GateVision PRO provides the designer of even the largest chips and SoCs with intuitive design navigation, netlist viewing, waveform viewing, logic cone extraction, interactive logic cone viewing for netlist debugging and design documentation.

Ultra Fast Netlist Viewer — GateVision PRO is an ultra fast and extreme capacity gate-level netlist debugger and netlist viewer reading and processing even the largest Verilog netlists, EDIF netlists and LEF/DEF netlists. Reading Verilog, EDIF and LEF/DEF netlists, GateVision PRO fits seamlessly into any design environment. Schematics are generated on the fly and the intuitive GUI lets the designer incrementally and easily navigate through the largest netlist files.

GateVision Screen Dump
Extreme performance netlist viewer for Verilog, EDIF, and LEF/DEF
Tcl based UserWare API — for advanced customization
32/64 bit database handles today′s largest SoCs, ASICs and FPGAs
Integrated Waveform Browser (accelerated VCD viewer)
Customizable path extraction engine finds critical paths
Cone view displays schematic fragments of critical areas
Intuitive GUI for ease of use
API — a tcl based UserWare API provides full access to the new 32/64-bit based database, for highly flexible customization. The designer can extend the functionality of GateVison PRO to meet the immediate needs of the project, adding, for example, electrical rule checking (ERC), report and documentation functions. The API also allows GateVison PRO to be closely integrated with different design flows and third party tools.

Waveform Viewer and Signal Tracing — GateVision PRO comes with a fully integrated waveform viewer and with support for interactive signal tracing in the source code, schematic view and waveform window. GateVision PRO compiles VCD simulation data into its own high-speed format for accelerated waveform browsing and signal tracing.

GateVision Screen Dump

32/64 Bit — exploiting the increasing powerful 64 bit platforms, Intel Xeon, Intel Core, AMD Opteron and AMD Phenom, GateVision PRO runs quickly and efficiently, even for the largest and most complex of today′s demanding ASICs, SoCs and FPGAs. The underlying database has been completely redesigned for 32/64-bit operation.

Logic cone — the GateVision PRO logic cone view provides interactive navigation within a schematic fragment, that portion of the circuit that is most relevant. This can be extended and reduced for signal path tracing through the complete design hierarchy.

Path extraction and Verilog Simulation — The customizable path extraction engine can automatically identify and extract critical paths in a design. These can be explored and cross-probed in different views to reduce both the complexity and time of the debug cycle. Path fragments can be exported as Verilog netlists for critical path Verilog simulation.

GateVision PRO Screen Dump

GUI — the intuitive GUI provides a host of facilities including context sensitive menus and multiple views. A powerful search tool provides quick access to any object or group of objects in a design, with the results stored in a result list. Listed objects can be highlighted or moved into the logic cone window.

Debugging Views — Built into GateVision Pro are a variety of view options, including schematic view, schematic fraction view, source code view, hierarchy tree view, waveform view, clock domain view, and object search view. Through these, and through cross-probing between views, it is easy to gain a deeper understanding of the device being debugged and to improve the debugging process.

Language: English
Operating Systems: Windows 7/8.x/10.x

Concept SpiceVision 6.10.5 Win/Linux

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Concept SpiceVision采用由许多EDA工具生成的复杂SPICE描述,并生成干净,易于读取的晶体管级原理图和电路片段,以及设计文档,以加速调试和项目开发。 Spice电路和模型是EDA世界的常见货币。 它们由许多EDA工具产生,并且提供对在组件的最低级别的电路的描述:晶体管,电容器,电阻器甚至互连,其组合以产生例如IC。 但除了最琐碎的设计,Spice文件很难阅读。 SpiceVision在屏幕上生成电路图,加快调试和项目开发。 SpiceVision产品系列有助于解决数字电路,混合信号ASIC,模拟电路,印刷电路板和MEMS的设计问题。


Concept SpiceVision 6.10.5/6.9.12/6.8.12 Win/Linux | 54.8 mb

Concept SpiceVision takes the complex SPICE descriptions produced by many EDA tools and generates clean, easy-to-read transistorlevel schematics and circuit fragments, and design documentation to speed up debugging and project development. Spice circuits and models are the common currency of the EDA world. They are generated by many EDA tools and provide a description of the circuit at the lowest level of components: the transistors, capacitors, resistors and even the interconnect, that combine to produce, for example, an IC. But for all but the most trivial design, Spice files are difficult to read. SpiceVision generates circuit schematics on screen and speeds up debugging and project development. The SpiceVision product family helps to solve design problems in: Digital Circuits, Mixed-Signal ASICs, Analog Circuits, Printed Circuit Boards and MEMS.

Language: English
Operating Systems: Windows 7/8.x/10.x/Linux

Concept RTLvision 6.10.5 Win/Linux

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Concept RTLvision PRO提供RTL的快速可视化,以便工程师可以轻松地了解和实现现有的代码元素,无论是在VHDL,Verilog还是系统Verilog。它不再可能从头开始执行所有ASIC和SoC设计:元素 先前的设计必须被重复使用,并且第三方IP块被非常频繁地嵌入。 但是了解第三方IP或遗留代码的RTL并不总是容易的,使得它耗费时间并且难以修改和集成到新的设计中。


Concept RTLvision 6.10.5/6.9.12/6.8.12 Win/Linux | 44.8 mb

Concept RTLvision PRO provides fast visualization of RTL, so that an engineer can easily understand, and implement existing code elements, whether in VHDL, Verilog or System Verilog.It is no longer possible to carry out all ASIC and SoC designs from scratch: elements of previous designs have to be re-used and third party IP blocks are embedded very often. But understanding the RTL for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design.

Language: English
Operating Systems: Windows 7/8.x/10.x 64bit

Concept StarVision 6.10.5 Win/Linux

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Concept StarVision PRO使工程师能够快速,轻松地了解和调试混合模式设计,并将IP构建块集成到其复杂的SoC和IC中。


Concept StarVision 6.10.5/6.9.12/6.8.12 Win/Linux | 47.8 mb

Concept StarVision PRO provides engineers with the ability to quickly and easily understand and debug mixed-mode designs and to integrate IP building blocks into their complex SoCs and ICs.
RTL, Gate-Level and SPICE-Level in one Integrated Debugging and Visualization Tool — Due to the increasing use of building blocks in SoC design, engineers need to work at different design levels (RTL, gate, transistor, analog, parasitic) as well as with different design languages and netlist formats. To support this challenge, Concept Engineering developed StarVision PRO, an integrated debugging cockpit for mixed-signal and digital design that makes analysis and debugging of complex SoC and IC designs easy and more transparent.
Easy Design Exploration — The interactive design navigation window shows schematic fragments of just the critical portion of the design while, at the same time, providing links to the original source code fragments (RTL, Netlist, SPICE) and to simulation results.

Language: English
Operating Systems: Windows 7/8.x/10.x/Linux

Optiwave OptiSystem 16.0 x64

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Optiwave OptiSystem 16.0 x64—光通讯和放大器设计套装

OptiSystem14.2修复并增强了几个元件的功能,包含新的前向误差修正(FEC)编码器元件和新的前向误差修正(FEC)解码器元件,模数转换(Analog to Digital)元件与数模转换(Digital to Analog)元件以及一个新的子系统库。主要新功能包括:

-引入了新的前向误差修正(FEC)编码器元件和新的前向误差修正(FEC)解码器元件以用于里所(Reed-Solomon)块码的编码与解码。

-电子均衡器(Electronic Equalizer)目前支持多级次(PAM)信号格式(可定义多级次信号阈值)的均衡化并能应用盲自适应法实现均衡化。

-升级了拉曼放大器-平均功率模型,拉曼放大器-稳态模型和双向光纤元件以支持多重拉曼增益效率文件(以波长值作为参考)的输入。

-升级了数转换(Analog to Digital)元件与数模转换(Digital to Analog)元件以支持随机(高斯)时间抖动以及微分非线性(DNL)损伤(高斯,一致性随机处理或者从输入文件定义)。

-将一个新的子系统(Subsystem)文件夹已经添加到了元件库中。现在用户可以使用鼠标拖放预定义子系统模型并对其进行修改以用于其项目设计之中。

新的库元件及增强

-信号传送器(Transmitters)与接收器(Receiver)设计:前向误差修正(FEC)解码器/编码器,模数转换元件(ADC)/数模转换元件(DAC)升级,LED/空间LED(Spatial LED)升级,电子扰动器(Electronic Jitter),电子均衡器(Electronic Equalizer)以及正交频分多路(OFDM)元件

-引入了新的前向误差修正(FEC)编码器元件和新的前向误差修正(FEC)解码器元件以用于里所(Reed-Solomon)块码的编码与解码。通过定义n和k参数来对不同的编码大小进行预分配(例如建议RS(255,239)在ITU-T G.709光传输网络中使用)。

-目前LED元件支持创建噪声收集器(Noise bins)并可单独的定义采样信号的采样率(带宽)和噪声收集器(Noise bins)。

-升级了空间LED(Spatial LED)元件以支持斜率效率功率计算方法并单独的定义噪声收集器(Noise bins)与采样信号的采样率。

-升级了正交频分多路解调元件和正交频分多路解调双偏振元件,以支持如下的调制格式: BPSK, QPSK, 8PSK, 16PSK, 8QAM (新),16QAM, 32QAM (新), 64QAM, 128QAM (新), 和 256QAM (新)。此外,目前还支持QAM调制格式;星状和圆状星座格式。

-电子扰动器元件包含了将抖动振幅定义为一个单位整数(unit-interval)函数或者单位整数百分比函数,并添加了一个新的“插值”参数以用于定义一个采样信号(线性或者三次样条曲线)的插值类型。

-升级后的模数转换元件和数模转换元件包含如下新的建模功能:
–添加了信号剪切(signal clipping)功能以用于定义最小和最大剪切振幅

–添加了高斯随机时间抖动功能以用于描述内部时钟抖动

–包含了微分非线性(DNL)损失模式以允许表征模数转换和数模转换电路中的非线性特性。微分非线性特性可以以一种高斯,一致性随机处理进行模拟或从一个输入文件中定义

–添加了新的图形以用于显示非线性畸变效应以及内部非线性特性(INL)

-电子均衡器(Electronic Equalizer)目前支持多级次(PAM)信号格式(可定义多级次信号阈值)的均衡化并能应用盲自适应法实现均衡化。
-放大器和光纤设计:拉曼放大器-平均功率模型,拉曼放大器-稳态模型和双向光纤元件

-升级了拉曼放大器-平均功率模型和拉曼放大器-稳态模型元件以支持多重拉曼增益效率文件(以波长值作为参考)的输入。


Optiwave OptiSystem 16.0/15.1/14.2 x64 (通讯和放大器设计) | 287 mb

OptiSystem 14.2 includes several new components and component enhancements including new Uniform FBG Sensor and WDM FBG Sensor Interrogator components, major updates to our Doped Fiber models, and enhancements to the functionality of several of our Electrical pulse generators.

Key New Features

• New Uniform FBG Sensor and WDM FBG Sensor Interrogator components have been added to our new Sensorsfolder. These new components allow for the characterization of fiber-based grating sensor systems.

• Functionality updates and enhancements to our steady state doped fiber models, including the Er Doped Fiber, Er-Yb Codoped Fiber, Yb Doped Fiber, Tm Doped Fiber, Pr Doped Fiber, and Ho Doped Fiber components (the last item is a new model addition to our doped fiber library)

• Functionality updates and enhancements to our dynamic doped fiber models, including the Er Doped Fiber Dynamic, Er-Yb Codoped Fiber Dynamic, Yb Doped Fiber Dynamic, Tm Doped Fiber Dynamic, and Ho Doped Fiber Dynamic(the last two items are new model additions to our fiber library)

Several of our electrical pulse generator components have been updated to allow for more flexibility in defining pulse sequences (components include the Hyperbolic-Secant Pulse Generator, Gaussian Pulse Generator, Triangle Pulse Generator, Saw-Up Pulse Generator, Saw-Down Pulse Generator, Impulse Generator, Raised Cosine Pulse Generator, Sine Pulse Generator, Measured Pulse, and Impulse Generator)

Language: English
Operating Systems: Windows 7/8.x 64Bit

NuHertz Filter Solutions 2019 v16.0

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Filter Solutions是一款基于PC平台的滤波器综合、分析软件包。请确保电脑上没有安装其他版本的Filter Solutions,否则会导致该版本无法使用。

它提供无源(集总参数滤波器和分布参数滤波器)、有源滤波器、计及寄生效应的开关电容电路、无限冲击响应(IIR,Infinite Impulse Response)和有限冲击响应(FIR,Finite Impulse Response)数字滤波器的分析和综合。


NuHertz Filter Solutions 2019 v16.0/2018 v15.6 (滤波器综合分析) | 154 mb


Nuhertz Technologies , a worldwide leader in low and high frequency filter syntheses and analyses, launches version 16.0 of Filter Solutions 2019 is a comprehensive PC based filter synthesis and analysis software package.

Filter Solutions provides passive (lumped and distributed), active, and switched capacitor circuit synthesis and modification analysis with parasitic effects, and digital filter IIR and FIR design with C code generation, and finite precision analysis.

Originally released in 1999, FilterSolutions has continued to develop and introduce new features. Nuhertz filter design software interoperability with best-in-class industry applications has been enhanced. Included in the linked programs are artwork generation tools, circuit simulators, S-Parameter component models and electromagnetic analyses programs.

Filter design software modules are used by design engineers in diverse disciplines such as communication systems, military electronics, medical, instrumentation, oil exploration and antenna design as well as for IC, MMIC and RFIC designs. Nuhertz is also the creator of Statmat and Spectra, programs for statistical analysis and digital data representation

Language: English
Operating Systems: Windows 7/8.x


NuHertz Filter Solutions 2015 v14.1.0 – Download Link (下载地址)
链接:https://pan.baidu.com/s/1Qf5mUN0szo_9SW_uYkPRfQ
密码:4znj

Motor-CAD 12.2.1

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Motor-CAD v12是专用于电机和发电机机电性能以及冷却的优化独特软件包最新版本。Motor-CAD最新的软件包集成了Mechanical机械设计模块和OPT优化设计模块,进一步丰富了解决方案。

关于Motor-CAD

电机CAD软件使电机设计人员能够在整个工作范围内评估电机拓扑和概念,并生产出针对性能,效率,尺寸和成本进行优化的设计。Motor-CAD集成化软件包,可在选型、设计阶段高效地对电机进行电磁和热、机械性能测试;软件包括:电磁(E-Magnetic)、热(Thermal)、机械(Mechanical)、优化(OPT)和虚拟实验室(Lab)五大模块,可快速精确评估电磁、热和机械特性 – 允许快速和迭代地执行多物理计算,因此用户可以在更短的时间内从概念到最终设计。

  • EMag:使用2D FE环境和分析算法的组合来快速计算电磁性能。使用我们广泛的参数化模板和几何图形,轻松优化设计。
  • Therm:电机热分析的行业标准工具,拥有超过20年的内置经验。在稳态和瞬态工作条件下计算电机组件的温度,并在计算的几秒钟内精确模拟热行为。
  • Lab::可在整个操作范围内快速准确地分析任何电机设计。在几分钟内完成效率映射和驾驶循环分析。
  • Mech:基于2D FEA的Motor-CAD解决方案,用于分析运行期间转子中的应力和位移(Motor-CAD v12中的新功能)。

精确的电磁和热计算可在几分钟内完成,使用户能够响应不断变化的规格,创新和探索整个设计空间。结果以易于理解的形式呈现,可以使用我们与其他软件的高级链接导出以集成到更大的工作流程中。

 

Motor-CAD v12中的新功能

Motor-CAD的发展受到强大的电动机设计工具的需求的驱动,该工具不断发展以满足用户的需求。一系列最新功能包括:

  • 带转子应力分析的新型机械模块 – 基于2D FEA的Motor-CAD解决方案,用于分析运行期间转子的应力和位移。
  • 用于有刷直流电机建模的新型PMDC EMag模块。
  • 用于单相感应电机建模的新型IM1PH EMag模块。
  • 改进的换热器模型,增加了与水套冷却系统的耦合。
  • 改进的实验室交流损耗图可在整个机器操作范围内提供更准确的损耗建模。
  • 新的自动生成报告 – 自动创建Microsoft Word格式的自定义报告,并提供用户选项以添加屏幕截图和值表。

要查看新功能的完整列表,请下载Motor-CAD v12规格表


Motor-CAD 12.2.1 (电机和发电机机电性能以及冷却优化)| 168 Mb

Motor-CAD v12 is the latest version of our unique software package dedicated to the electromechanical performance of motors and generators and the optimisation of their cooling.

About Motor-CAD

Motor-CAD software enables motor designers to evaluate motor topologies and concepts across the full operating range and produce designs that are optimised for performance, efficiency, size and cost. The software’s four integrated modules—EMag, Therm, Lab and Mech—allow multi-physics calculations to be performed quickly and iteratively, so users can get from concept to final design in less time.

  • EMag: Uses a combination of 2D FE environment and analytical algorithms for fast calculation of electromagnetic performance. Optimise designs easily with our extensive range of parameterised templates and geometries.
  • Therm: The industry-standard tool for thermal analysis of electric machines, with over 20 years of inbuilt experience. Calculate the temperature of the motor components in steady-state and transient operating conditions and accurately model thermal behaviour within seconds of calculation.
  • Lab: Enables rapid and accurate analysis of any electric machine design over the full operating envelope. Carry out efficiency mapping and drive cycle analysis within minutes.
  • Mech: 2D FEA based solution in Motor-CAD to analyse stress and displacement in rotors during operation (new in Motor-CAD v12).

Accurate electromagnetic and thermal calculations can be performed in minutes, allowing users to respond to changing specifications, innovate and explore the whole design space. The results are presented in an easy to understand form for analysis and can be exported for integration into larger workflows using our advanced links to other software.

New features in Motor-CAD v12

The development of Motor-CAD is driven by demand for a powerful electric motor design tool that evolves to keep up with the needs of its users. A selection of the latest features includes:

  • New mechanical module with rotor stress analysis — 2D FEA based solution in Motor-CAD to analyse stress and displacement in rotors during operation.
  • New PMDC EMag module for modelling of brushed DC machines.
  • New IM1PH EMag module for modelling of single phase induction machines.
  • Improved Heat Exchanger Model with added coupling to water jacket cooling systems.
  • Improved Lab AC loss map giving more accurate loss modelling across whole machine operating range.
  • New automatic report generation – automatically create custom reports in Microsoft Word format, with user options to add screenshots and tables of values.

To see the full list of new features, download Motor-CAD v12 specification sheet.

HomePage: http://www.motor-design.com
Language: English/简体中文
Operating Systems: Windows 7/8.x

Keysight Model Builder Program (MBP) 2019 x64

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Model Builder Program (MBP) 2019 介绍了用于静态随机存取存储器(SRAM)单元的新模型提取套件。自动化模型提取流程针对静态模型和紧凑模型进行了增强,包括 BSIM3v3、BSIM4 和 BSIM-CMG。Script API 获得更新,可以支持更多功能。用户界面(UI)也进行了众多改进。内部 SPICE 引擎支持最新的模型版本:BSIM-CMG 110.0、109.0,BSIM-IMG 102.8、102.7,HiSIM2 2.9.0,HiSIM_HV 2.3.2、2.3.1、2.3.0 和 EKV 302.00。


Keysight Model Builder Program (MBP) 2019/2017.2 x64 (模型质量检验)| 775 Mb

Model Builder Program (MBP) is a one-stop solution that provides both automation and flexibility for high-volume model generation. MBP includes automated extraction packages for industry standard models as well as an open interface for modeling strategy customization. Turnkey solutions are also provided for the advanced statistical and mismatch model extraction, layout proximity effects (LPE) modeling, static random access memory (SRAM) cell modeling, HVMOS modeling, scalable Inductor modeling and corner library generation.

Key Benefits of MBP
– Automated extraction packages and the internal engine to increase modeling productivity.
– Script environment to increase the flexibility for customization.
– User friendly GUI and a rich set of modeling utilities to further increase the working efficiency and improve model quality.

Language: English
Operating Systems: Windows 7/8.x 64Bit

Keysight Model Quality Assurance (MQA) 2019 x64

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Model Quality Assurance(MQA)是一款自动化的 SPICE 模型验证软件,支持您检查和分析 SPICE 模型库,比较不同的模型,以及全面和高效地生成质量检验(QA)报告。经过 10 多年的发展,MQA 已经成为 SPICE 模型验收和签核的行业标准,在领先的集成器件制造商(IDM)、代工厂和设计公司中得到广泛采用。

MQA 的关键优势
– 完全自动化的模型质量检验和报告流程,帮助您提高效率
– 通过定制的知识型检查例程,让您轻松识别模型问题
– 确保您的 EDA 环境在各个代工厂、技术、制程节点和仿真器之间保持一致性
MQA 2017 添加了新的内部 SPICE3 仿真器,用于快速仿真和快速模型质量检验(QA)。支持 Python 脚本,可以自动生成定制的 Excel 表格。新版本支持 Spectre 本地老化仿真和最新的 SmartSpice 版本。检查功能和规则获得了更新,可以支持高级阱邻近效应(WPE)和热噪声质量检验(QA)。MQA 2017 还支持 Microsoft Office 2016 来进行文档编辑和报告。


Keysight Model Quality Assurance (MQA) 2019/2017.2 x64 (模型质量检验)| 775 Mb

Model Quality Assurance (MQA) is an automated SPICE model validation software which allows you to check and analyze SPICE model library, compare different models, and generate quality assurance (QA) reports in a complete and efficient way. With more than ten years of history, MQA has become the industry standard for SPICE model acceptance and signoff and is widely adopted by leading integrated device manufacturers (IDMs), foundries and design houses.

Key Benefits of MQA
– Fully automatic model quality assurance and reporting process to improve the productivity
– Easily to identify the model issues with the customizable knowledge-based checking routines
– Ensure your EDA environment compliance across various foundries, technologies, process nodes and simulators

Language: English
Operating Systems: Windows 7/8.x 64Bit

 

Synopsys Synplify FPGA 2018.09 SP1 Win/Linux

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Synplify FPGA包含可选Synplify Pro和Synplify Premier FPGA综合工具。
Synopsys Synplify FPGA设计软件提供了一个高品质,高性能和易于使用的FPGA实现和调试环境。采用Synopsys的FPGA工具套件增益设计师快速进入超结果为复杂的FPGA,面积优化成本和降低功耗,自动化软错误缓解,分层设计能力和多FPGA厂商的支持。该的Synplify Pro和Synplify Premier FPGA设计工具,通过提供链接到高性能功能验证与VCS仿真和集成Synphony模型编译器的信号处理硬件的高层次综合提供额外的价值。
许多设计和验证团队越来越倾向于使用基于 FPGA 的原型验证,以便使产品及时进入市场。 基于 FPGA 的 Synopsys 原型验证解决方案可以使开发者尽早进行芯片制造前的嵌入式软件开发和软硬件协同设计,从而缩短上市时间并降低昂贵的器件改版费用。 同时,我们紧密集成且易于使用的HAPS硬件和软件工具套件可大幅加快从单个 IP 模块到处理器子系统再到整个SoC的软件开发、软硬件集成和系统验证。


Synopsys Synplify FPGA 2017.09/2018.09 SP1 Win/Linux (FPGA综合工具) | 1097 Mb
点击放大完整功能测试图片

Synplify Premier solution is the industry’s most productive FPGA implementation and debug environment. It includes all the features of Synplify Pro and additionally provides a comprehensive suite of tools and technologies for advanced FPGA designers as well as ASIC prototypers targeting single FPGA-based prototypes.
The Synplify Premier software delivers fast turnaround time capabilities and feedback for users seeking to quickly implement the design on the board or to tune their design projects prior to final implementation. It addresses the most challenging aspects of FPGA design including timing closure and has the ability to perform graph-based physical synthesis for more accurate upfront timing prediction. It provides flows for fast logic verification and RT-Level debug. Under the hood, it contains optimization techniques that enhance DSP, IP and embedded design results. For ASIC prototypers, it delivers ASIC design file and DesignWare compatibility as well as tight integration with the Confirma Rapid Prototyping platform and FPGA vendor back-end tools as well as vendor embedded tools including Altera SoPC Builder and Xilinx EDK.
The Synplify Premier product offers FPGA Designers and ASIC Prototypers, targeting single FPGA-based prototypes, with the most efficient method of design implementation and debug. The Synplify Premier software provides in-system verification of FPGAs, dramatically accelerates the debug process, and provides a rapid and incremental method for finding elusive design problems.
The Synplify Premier software advantages include:
* technology and vendor independence
* in-system debug
* fast timing closure
* RTL analysis
* DSP-friendly synthesis algorithms
* superior Quality of Results (QoR)

Language: English
Operating Systems: Windows 7/8.x/10.x/RHEL 6.6+, 7.x/SLES 11.x and 12.x